Entity: otbn_lsu Diagram int DmemSizeByte int DmemAddrWidth clk_i rst_ni [ExtWLEN-1:0] dmem_rdata_i dmem_rvalid_i dmem_rerror_i lsu_load_req_i lsu_store_req_i insn_subset_e lsu_req_subset_i [DmemAddrWidth-1:0] lsu_addr_i [BaseIntgWidth-1:0] lsu_base_wdata_i [ExtWLEN-1:0] lsu_bignum_wdata_i dmem_req_o dmem_write_o [DmemAddrWidth-1:0] dmem_addr_o [ExtWLEN-1:0] dmem_wdata_o [ExtWLEN-1:0] dmem_wmask_o [BaseWordsPerWLEN-1:0] dmem_rmask_o [BaseIntgWidth-1:0] lsu_base_rdata_o [ExtWLEN-1:0] lsu_bignum_rdata_o lsu_rdata_err_o
Description Copyright lowRISC contributors. Licensed under the Apache License, Version 2.0, see LICENSE for details. SPDX-License-Identifier: Apache-2.0 *
Generics
Generic name
Type
Value
Description
DmemSizeByte
int
4096
DmemAddrWidth
int
prim_util_pkg::vbits(DmemSizeByte)
Ports
Port name
Direction
Type
Description
clk_i
input
rst_ni
input
dmem_req_o
output
Data memory (DMEM) interface
dmem_write_o
output
dmem_addr_o
output
[DmemAddrWidth-1:0]
dmem_wdata_o
output
[ExtWLEN-1:0]
dmem_wmask_o
output
[ExtWLEN-1:0]
dmem_rmask_o
output
[BaseWordsPerWLEN-1:0]
dmem_rdata_i
input
[ExtWLEN-1:0]
dmem_rvalid_i
input
dmem_rerror_i
input
lsu_load_req_i
input
lsu_store_req_i
input
lsu_req_subset_i
input
insn_subset_e
lsu_addr_i
input
[DmemAddrWidth-1:0]
lsu_base_wdata_i
input
[BaseIntgWidth-1:0]
lsu_bignum_wdata_i
input
[ExtWLEN-1:0]
lsu_base_rdata_o
output
[BaseIntgWidth-1:0]
lsu_bignum_rdata_o
output
[ExtWLEN-1:0]
lsu_rdata_err_o
output
Signals
Name
Type
Description
lsu_word_select
logic [BaseWordAddrW-1:2]
lsu_word_select_en
logic
unused_clk
logic
clk_i, rst_ni are only used by assertions
unused_rst_n
logic
Constants
Name
Type
Value
Description
DmemAddrWidth
int
prim_util_pkg::vbits(DmemSizeByte)
BaseWordsPerWLen
int
WLEN / 32
BaseWordAddrW
int
prim_util_pkg::vbits(WLEN/8
Functions
wmask_from_word_addr (logic [BaseWordAddrW-1:2]) return (logic [ExtWLEN-1:0])
Description
rmask_from_word_addr (logic [BaseWordAddrW-1:2]) return (logic [BaseWordsPerWLEN-1:0])
Processes
unnamed: ( @(posedge clk_i) )