Package: otbn_pkg

Description

Copyright lowRISC contributors.
Licensed under the Apache License, Version 2.0, see LICENSE for details.
SPDX-License-Identifier: Apache-2.0

Constants

Name Type Value Description
WLEN int 256
ExtWLEN int WLEN * 39 / 32 "Extended" WLEN: the size of the datapath with added integrity bits
BaseIntgWidth int 39 Width of base (32b) data path with added integrity bits
BaseWordsPerWLEN int WLEN / 32 Number of 32-bit words per WLEN
NFlagGroups int 2 Number of flag groups
GprAw int 5 Width of the GPR index/address
NGpr int 2 ** GprAw Number of General Purpose Registers (GPRs)
WdrAw int 5 Width of the WDR index/address
NWdr int 2 ** WdrAw Number of Wide Data Registers (WDRs)
EdnDataWidth int 256 Width of entropy input
AlertFatal int 0 Toplevel constants ============================================================================
AlertRecov int 1
CsrNumWidth int 12 Control and Status Registers (CSRs)
NWsr int 4 Number of WSRs
WsrNumWidth int $clog2(NWsr)
NIspr int 5 Internal Special Purpose Registers (ISPRs) CSRs and WSRs have some overlap into what they map into. ISPRs are the actual registers in the design which CSRs and WSRs are mapped on to.
IsprNumWidth int $clog2(NIspr)
FlagsWidth int $bits(flags_t)
UrndLfsrWidth int 256 URNG PRNG default LFSR seed and permutation A single default seed is split into 64 bit chunks, a separate LFSR is used for each chunk. All LFSR chunks use the same permutation. These LFSR parameters have been generated with $ ./util/design/gen-lfsr-seed.py --width 256 --seed 2840984437 --prefix "Urnd"
urnd_lfsr_seed_t urnd_lfsr_seed_t 256'h84ddfadaf7e1134d70aa1c59de6197ff25a4fe335d095f1e2cba89acbe4a07e9
UrndChunkLfsrWidth int 64 These LFSR parameters have been generated with $ ./util/design/gen-lfsr-seed.py --width 64 --seed 2840984437 --prefix "UrndChunk"
urnd_chunk_lfsr_perm_t urnd_chunk_lfsr_perm_t
otp_ctrl_pkg otp_ctrl_pkg::otbn_key_t 128'h14e8cecae3040d5e12286bb3cc113298
otp_ctrl_pkg otp_ctrl_pkg::otbn_nonce_t 64'hf79780bc735f3843

Types

Name Type Description
regfile_e enum integer {
RegFileFF = 0,
RegFileFPGA = 1 }		 Register file implementation selection enum.
cmd_e enum logic [7:0] {
CmdExecute = 8'h01,
CmdSecWipeDmem = 8'h02,
CmdSecWipeImem = 8'h03 }		 Command to execute. See the CMD register description in otbn.hjson for details.
status_e enum logic [7:0] {
StatusIdle = 8'h00,
StatusBusyExecute = 8'h01,
StatusBusySecWipeDmem = 8'h02,
StatusBusySecWipeImem = 8'h03,
StatusLocked = 8'hFF }		 Status register values. See the STATUS register description in otbn.hjson for details.
err_bits_t struct packed {
logic fatal_lifecycle_escalation;
logic fatal_illegal_bus_access;
logic fatal_reg;
logic fatal_dmem;
logic fatal_imem;
logic loop;
logic illegal_insn;
logic call_stack;
logic bad_insn_addr;
logic bad_data_addr;
}		 Error bits
Note: These errors are duplicated in other places. If updating them here, update those too.
insn_subset_e enum logic {
InsnSubsetBase = 1'b0,
InsnSubsetBignum = 1'b1 }		 Constants =====================================================================================
insn_opcode_e enum logic [6:0] {
InsnOpcodeBaseLoad = 7'h03,
InsnOpcodeBaseMemMisc = 7'h0f,
InsnOpcodeBaseOpImm = 7'h13,
InsnOpcodeBaseAuipc = 7'h17,
InsnOpcodeBaseStore = 7'h23,
InsnOpcodeBaseOp = 7'h33,
InsnOpcodeBaseLui = 7'h37,
InsnOpcodeBaseBranch = 7'h63,
InsnOpcodeBaseJalr = 7'h67,
InsnOpcodeBaseJal = 7'h6f,
InsnOpcodeBaseSystem = 7'h73,
InsnOpcodeBignumMisc = 7'h0B,
InsnOpcodeBignumArith = 7'h2B,
InsnOpcodeBignumMulqacc = 7'h3B,
InsnOpcodeBignumBaseMisc = 7'h7B }		 Opcodes (field [6:0] in the instruction), matching the RISC-V specification for the base instruction subset.
alu_op_base_e enum logic [3:0] {
AluOpBaseAdd,
AluOpBaseSub,
AluOpBaseXor,
AluOpBaseOr,
AluOpBaseAnd,
AluOpBaseNot,
AluOpBaseSra,
AluOpBaseSrl,
AluOpBaseSll }
alu_op_bignum_e enum logic [3:0] {
AluOpBignumAdd,
AluOpBignumAddc,
AluOpBignumAddm,
AluOpBignumSub,
AluOpBignumSubb,
AluOpBignumSubm,
AluOpBignumRshi,
AluOpBignumXor,
AluOpBignumOr,
AluOpBignumAnd,
AluOpBignumNot }		 TODO: Can we arrange this to simplify decoding logic?
comparison_op_base_e enum logic {
ComparisonOpBaseEq,
ComparisonOpBaseNeq }
op_a_sel_e enum logic [1:0] {
OpASelRegister = 'd0,
OpASelZero = 'd1,
OpASelCurrPc = 'd2 }		 Operand a source selection
op_b_sel_e enum logic {
OpBSelRegister = 'd0,
OpBSelImmediate = 'd1 }		 Operand b source selection
imm_b_sel_base_e enum logic [2:0] {
ImmBaseBI,
ImmBaseBS,
ImmBaseBB,
ImmBaseBU,
ImmBaseBJ,
ImmBaseBL,
ImmBaseBX }		 Immediate b selection for base ISA
shamt_sel_bignum_e enum logic [1:0] {
ShamtSelBignumA,
ShamtSelBignumS,
ShamtSelBignumZero }		 Shift amount select for bignum ISA
rf_wd_sel_e enum logic [2:0] {
RfWdSelEx,
RfWdSelNextPc,
RfWdSelLsu,
RfWdSelIspr,
RfWdSelIncr,
RfWdSelMac,
RfWdSelMovSel }		 Regfile write data selection
csr_e enum logic [CsrNumWidth-1:0] {
CsrFg0 = 12'h7C0,
CsrFg1 = 12'h7C1,
CsrFlags = 12'h7C8,
CsrMod0 = 12'h7D0,
CsrMod1 = 12'h7D1,
CsrMod2 = 12'h7D2,
CsrMod3 = 12'h7D3,
CsrMod4 = 12'h7D4,
CsrMod5 = 12'h7D5,
CsrMod6 = 12'h7D6,
CsrMod7 = 12'h7D7,
CsrRndPrefetch = 12'h7D8,
CsrRnd = 12'hFC0,
CsrUrnd = 12'hFC1 }
wsr_e enum logic [WsrNumWidth-1:0] {
WsrMod = 'd0,
WsrRnd = 'd1,
WsrUrnd = 'd2,
WsrAcc = 'd3 }
ispr_e enum logic [IsprNumWidth-1:0] {
IsprMod = 'd0,
IsprRnd = 'd1,
IsprAcc = 'd2,
IsprFlags = 'd3,
IsprUrnd = 'd4 }
flag_group_t logic [$clog2(NFlagGroups)-1:0]
flags_t struct packed {
logic Z;
logic L;
logic M;
logic C;
}
flag_e enum logic [$clog2(FlagsWidth)-1:0] {
FlagC = 'd0,
FlagM = 'd1,
FlagL = 'd2,
FlagZ = 'd3 }
insn_dec_shared_t struct packed {
insn_subset_e subset;
logic ecall_insn;
logic ld_insn;
logic st_insn;
logic branch_insn;
logic jump_insn;
logic loop_insn;
logic ispr_rd_insn;
logic ispr_wr_insn;
logic ispr_rs_insn;
}		 TODO: Figure out how to add assertions for the enum type width; initial blocks, as produced by ASSERT_INIT, aren't allowed in packages. `ASSERT_INIT(WsrESizeMatchesParameter_A, $bits(wsr_e) == WsrNumWidth) Structures for decoded instructions, grouped into three: - insn_dec_shared_t - Anything that applies to both bignum and base microarchitecture - insn_dec_base_t - Anything that only applies to the base side microarchitecture - insn_dec_bignum_t - Anything that only applies to bignum side microarchitecture
TODO: The variable names are rather short, especially "i" is confusing. Think about renaming.
insn_dec_base_t struct packed {
logic [4:0] d;
logic [4:0] a;
logic [4:0] b;
logic [31:0] i;
alu_op_base_e alu_op;
comparison_op_base_e comparison_op;
op_a_sel_e op_a_sel;
op_b_sel_e op_b_sel;
logic rf_ren_a;
logic rf_ren_b;
logic rf_we;
rf_wd_sel_e rf_wdata_sel;
logic [11:0] loop_bodysize;
logic loop_immediate;
}
insn_dec_bignum_t struct packed {
logic [WdrAw-1:0] d;
logic [WdrAw-1:0] a;
logic [WdrAw-1:0] b;
logic [WLEN-1:0] i;
logic rf_a_indirect;
logic rf_b_indirect;
logic rf_d_indirect;
logic d_inc;
logic a_inc;
logic a_wlen_word_inc;
logic b_inc;
logic [$clog2(WLEN)-1:0] alu_shift_amt;
logic alu_shift_right;
flag_group_t alu_flag_group;
flag_e alu_sel_flag;
logic alu_flag_en;
logic mac_flag_en;
alu_op_bignum_e alu_op;
op_b_sel_e alu_op_b_sel;
logic [1:0] mac_op_a_qw_sel;
logic [1:0] mac_op_b_qw_sel;
logic mac_wr_hw_sel_upper;
logic [1:0] mac_pre_acc_shift;
logic mac_zero_acc;
logic mac_shift_out;
logic mac_en;
logic rf_we;
rf_wd_sel_e rf_wdata_sel;
logic rf_ren_a;
logic rf_ren_b;
logic sel_insn;
}
alu_base_operation_t struct packed {
alu_op_base_e op;
logic [31:0] operand_a;
logic [31:0] operand_b;
}
alu_base_comparison_t struct packed {
comparison_op_base_e op;
logic [31:0] operand_a;
logic [31:0] operand_b;
}
alu_bignum_operation_t struct packed {
alu_op_bignum_e op;
logic [WLEN-1:0] operand_a;
logic [WLEN-1:0] operand_b;
logic shift_right;
logic [$clog2(WLEN)-1:0] shift_amt;
flag_group_t flag_group;
flag_e sel_flag;
logic alu_flag_en;
logic mac_flag_en;
}
mac_bignum_operation_t struct packed {
logic [WLEN-1:0] operand_a;
logic [WLEN-1:0] operand_b;
logic [1:0] operand_a_qw_sel;
logic [1:0] operand_b_qw_sel;
logic wr_hw_sel_upper;
logic [1:0] pre_acc_shift_imm;
logic zero_acc;
logic shift_acc;
}
otbn_state_e enum logic [1:0] {
OtbnStateHalt,
OtbnStateUrndRefresh,
OtbnStateRun,
OtbnStateStall }		 States for controller state machine
otbn_start_stop_state_e enum logic [1:0] {
OtbnStartStopStateHalt,
OtbnStartStopStateUrndRefresh,
OtbnStartStopStateRunning }
urnd_lfsr_seed_t logic [UrndLfsrWidth-1:0]
urnd_chunk_lfsr_perm_t logic [UrndChunkLfsrWidth-1:0][$clog2(UrndChunkLfsrWidth)-1:0]
otbn_dmem_nonce_t logic [63:0]
otbn_imem_nonce_t logic [63:0]