Entity: otbn_reg_top

• File: otbn_reg_top.sv

Diagram

Description

Ports

Port name	Direction	Type	Description
clk_i	input
rst_ni	input
tl_i	input
tl_o	output
tl_win_o	output		Output port for window
tl_win_i	input
reg2hw	output		Write
hw2reg	input		Read
intg_err_o	output		Integrity check errors
devmode_i	input		If 1, explicit error return for unmapped register access

Signals

Name	Type	Description
reg_we	logic	register signals
reg_re	logic
reg_addr	logic [AW-1:0]
reg_wdata	logic [DW-1:0]
reg_be	logic [DBW-1:0]
reg_rdata	logic [DW-1:0]
reg_error	logic
addrmiss	logic
wr_err	logic
reg_rdata_next	logic [DW-1:0]
reg_busy	logic
tl_reg_h2d	tlul_pkg::tl_h2d_t
tl_reg_d2h	tlul_pkg::tl_d2h_t
intg_err	logic	incoming payload check
intg_err_q	logic
tl_o_pre	tlul_pkg::tl_d2h_t	outgoing integrity generation
tl_socket_h2d	tlul_pkg::tl_h2d_t
tl_socket_d2h	tlul_pkg::tl_d2h_t
reg_steer	logic [1:0]
intr_state_we	logic	Define SW related signals Format: {wd
intr_state_qs	logic
intr_state_wd	logic
intr_enable_we	logic
intr_enable_qs	logic
intr_enable_wd	logic
intr_test_we	logic
intr_test_wd	logic
alert_test_we	logic
alert_test_fatal_wd	logic
alert_test_recov_wd	logic
cmd_we	logic
cmd_wd	logic [7:0]
status_re	logic
status_qs	logic [7:0]
err_bits_bad_data_addr_qs	logic
err_bits_bad_insn_addr_qs	logic
err_bits_call_stack_qs	logic
err_bits_illegal_insn_qs	logic
err_bits_loop_qs	logic
err_bits_fatal_imem_qs	logic
err_bits_fatal_dmem_qs	logic
err_bits_fatal_reg_qs	logic
err_bits_fatal_illegal_bus_access_qs	logic
err_bits_fatal_lifecycle_escalation_qs	logic
start_addr_we	logic
start_addr_wd	logic [31:0]
fatal_alert_cause_bus_integrity_error_qs	logic
fatal_alert_cause_imem_error_qs	logic
fatal_alert_cause_dmem_error_qs	logic
fatal_alert_cause_reg_error_qs	logic
fatal_alert_cause_illegal_bus_access_qs	logic
fatal_alert_cause_lifecycle_escalation_qs	logic
insn_cnt_re	logic
insn_cnt_qs	logic [31:0]
addr_hit	logic [9:0]
shadow_busy	logic	shadow busy
reg_busy_sel	logic	register busy
unused_wdata	logic	Unused signal tieoff wdata / byte enable are not always fully used add a blanket unused statement to handle lint waivers
unused_be	logic

Constants

Name	Type	Value	Description
AW	int	16
DW	int	32
DBW	int	DW/8	Byte Width

Processes

• unnamed: ( @(posedge clk_i or negedge rst_ni) )

• unnamed: ( )

• unnamed: ( )

• unnamed: ( )

• unnamed: ( )

• unnamed: ( )

Instantiations

• u_chk: tlul_cmd_intg_chk

• u_rsp_intg_gen: tlul_rsp_intg_gen

• u_socket: tlul_socket_1n

• u_reg_if: tlul_adapter_reg

• u_intr_state: prim_subreg

• u_intr_enable: prim_subreg

• u_intr_test: prim_subreg_ext

• u_alert_test_fatal: prim_subreg_ext

• u_alert_test_recov: prim_subreg_ext

• u_cmd: prim_subreg_ext

• u_status: prim_subreg_ext

• u_err_bits_bad_data_addr: prim_subreg

• u_err_bits_bad_insn_addr: prim_subreg

• u_err_bits_call_stack: prim_subreg

• u_err_bits_illegal_insn: prim_subreg

• u_err_bits_loop: prim_subreg

• u_err_bits_fatal_imem: prim_subreg

• u_err_bits_fatal_dmem: prim_subreg

• u_err_bits_fatal_reg: prim_subreg

• u_err_bits_fatal_illegal_bus_access: prim_subreg

• u_err_bits_fatal_lifecycle_escalation: prim_subreg

• u_start_addr: prim_subreg

• u_fatal_alert_cause_bus_integrity_error: prim_subreg

• u_fatal_alert_cause_imem_error: prim_subreg

• u_fatal_alert_cause_dmem_error: prim_subreg

• u_fatal_alert_cause_reg_error: prim_subreg

• u_fatal_alert_cause_illegal_bus_access: prim_subreg

• u_fatal_alert_cause_lifecycle_escalation: prim_subreg

• u_insn_cnt: prim_subreg_ext