Package: otp_ctrl_reg_pkg

Description

Copyright lowRISC contributors.
Licensed under the Apache License, Version 2.0, see LICENSE for details.
SPDX-License-Identifier: Apache-2.0

Register Package auto-generated by reggen containing data structure

Constants

Name Type Value Description
NumSramKeyReqSlots int 2
OtpByteAddrWidth int 11
NumErrorEntries int 10
NumDaiWords int 2
NumDigestWords int 2
NumSwCfgWindowWords int 512
NumDebugWindowWords int 16
NumPart int 8
VendorTestOffset int 0
VendorTestSize int 64
ScratchOffset int 0
ScratchSize int 56
VendorTestDigestOffset int 56
VendorTestDigestSize int 8
CreatorSwCfgOffset int 64
CreatorSwCfgSize int 768
CreatorSwCfgAstCfgOffset int 64
CreatorSwCfgAstCfgSize int 256
CreatorSwCfgRomExtSkuOffset int 320
CreatorSwCfgRomExtSkuSize int 4
CreatorSwCfgUseSwRsaVerifyOffset int 324
CreatorSwCfgUseSwRsaVerifySize int 4
CreatorSwCfgKeyIsValidOffset int 328
CreatorSwCfgKeyIsValidSize int 8
CreatorSwCfgDigestOffset int 824
CreatorSwCfgDigestSize int 8
OwnerSwCfgOffset int 832
OwnerSwCfgSize int 768
RomErrorReportingOffset int 832
RomErrorReportingSize int 4
RomBootstrapEnOffset int 836
RomBootstrapEnSize int 4
RomFaultResponseOffset int 840
RomFaultResponseSize int 4
RomAlertClassEnOffset int 844
RomAlertClassEnSize int 4
RomAlertEscalationOffset int 848
RomAlertEscalationSize int 4
RomAlertClassificationOffset int 852
RomAlertClassificationSize int 320
RomLocalAlertClassificationOffset int 1172
RomLocalAlertClassificationSize int 64
RomAlertAccumThreshOffset int 1236
RomAlertAccumThreshSize int 16
RomAlertTimeoutCyclesOffset int 1252
RomAlertTimeoutCyclesSize int 16
RomAlertPhaseCyclesOffset int 1268
RomAlertPhaseCyclesSize int 64
OwnerSwCfgDigestOffset int 1592
OwnerSwCfgDigestSize int 8
HwCfgOffset int 1600
HwCfgSize int 80
DeviceIdOffset int 1600
DeviceIdSize int 32
ManufStateOffset int 1632
ManufStateSize int 32
EnSramIfetchOffset int 1664
EnSramIfetchSize int 1
EnCsrngSwAppReadOffset int 1665
EnCsrngSwAppReadSize int 1
EnEntropySrcFwReadOffset int 1666
EnEntropySrcFwReadSize int 1
EnEntropySrcFwOverOffset int 1667
EnEntropySrcFwOverSize int 1
HwCfgDigestOffset int 1672
HwCfgDigestSize int 8
Secret0Offset int 1680
Secret0Size int 40
TestUnlockTokenOffset int 1680
TestUnlockTokenSize int 16
TestExitTokenOffset int 1696
TestExitTokenSize int 16
Secret0DigestOffset int 1712
Secret0DigestSize int 8
Secret1Offset int 1720
Secret1Size int 88
FlashAddrKeySeedOffset int 1720
FlashAddrKeySeedSize int 32
FlashDataKeySeedOffset int 1752
FlashDataKeySeedSize int 32
SramDataKeySeedOffset int 1784
SramDataKeySeedSize int 16
Secret1DigestOffset int 1800
Secret1DigestSize int 8
Secret2Offset int 1808
Secret2Size int 88
RmaTokenOffset int 1808
RmaTokenSize int 16
CreatorRootKeyShare0Offset int 1824
CreatorRootKeyShare0Size int 32
CreatorRootKeyShare1Offset int 1856
CreatorRootKeyShare1Size int 32
Secret2DigestOffset int 1888
Secret2DigestSize int 8
LifeCycleOffset int 1896
LifeCycleSize int 88
LcTransitionCntOffset int 1896
LcTransitionCntSize int 48
LcStateOffset int 1944
LcStateSize int 40
NumAlerts int 3
CoreAw int 13 Address widths within the block
PrimAw int 1
CoreAw logic [CoreAw-1:0] undefined Register offsets for core interface
CoreAw logic [CoreAw-1:0] 4
CoreAw logic [CoreAw-1:0] 8
CoreAw logic [CoreAw-1:0] c
CoreAw logic [CoreAw-1:0] 10
CoreAw logic [CoreAw-1:0] 14
CoreAw logic [CoreAw-1:0] 18
CoreAw logic [CoreAw-1:0] c
CoreAw logic [CoreAw-1:0] 20
CoreAw logic [CoreAw-1:0] 24
CoreAw logic [CoreAw-1:0] 28
CoreAw logic [CoreAw-1:0] c
CoreAw logic [CoreAw-1:0] 30
CoreAw logic [CoreAw-1:0] 34
CoreAw logic [CoreAw-1:0] 38
CoreAw logic [CoreAw-1:0] c
CoreAw logic [CoreAw-1:0] 40
CoreAw logic [CoreAw-1:0] 44
CoreAw logic [CoreAw-1:0] 48
CoreAw logic [CoreAw-1:0] c
CoreAw logic [CoreAw-1:0] 50
CoreAw logic [CoreAw-1:0] 54
CoreAw logic [CoreAw-1:0] 58
CoreAw logic [CoreAw-1:0] c
CoreAw logic [CoreAw-1:0] 60
CoreAw logic [CoreAw-1:0] 64
CoreAw logic [CoreAw-1:0] 68
CoreAw logic [CoreAw-1:0] c
CoreAw logic [CoreAw-1:0] 70
CoreAw logic [CoreAw-1:0] 74
CoreAw logic [CoreAw-1:0] 78
CoreAw logic [CoreAw-1:0] c
CoreAw logic [CoreAw-1:0] 80
CoreAw logic [CoreAw-1:0] 84
CoreAw logic [CoreAw-1:0] 88
CoreAw logic [CoreAw-1:0] c
OTP_CTRL_INTR_TEST_RESVAL logic [1:0] undefined Reset values for hwext registers and their fields for core interface
OTP_CTRL_INTR_TEST_OTP_OPERATION_DONE_RESVAL logic [0:0] undefined
OTP_CTRL_INTR_TEST_OTP_ERROR_RESVAL logic [0:0] undefined
OTP_CTRL_ALERT_TEST_RESVAL logic [2:0] undefined
OTP_CTRL_ALERT_TEST_FATAL_MACRO_ERROR_RESVAL logic [0:0] undefined
OTP_CTRL_ALERT_TEST_FATAL_CHECK_ERROR_RESVAL logic [0:0] undefined
OTP_CTRL_ALERT_TEST_FATAL_BUS_INTEG_ERROR_RESVAL logic [0:0] undefined
OTP_CTRL_STATUS_RESVAL logic [16:0] undefined
OTP_CTRL_STATUS_VENDOR_TEST_ERROR_RESVAL logic [0:0] undefined
OTP_CTRL_STATUS_CREATOR_SW_CFG_ERROR_RESVAL logic [0:0] undefined
OTP_CTRL_STATUS_OWNER_SW_CFG_ERROR_RESVAL logic [0:0] undefined
OTP_CTRL_STATUS_HW_CFG_ERROR_RESVAL logic [0:0] undefined
OTP_CTRL_STATUS_SECRET0_ERROR_RESVAL logic [0:0] undefined
OTP_CTRL_STATUS_SECRET1_ERROR_RESVAL logic [0:0] undefined
OTP_CTRL_STATUS_SECRET2_ERROR_RESVAL logic [0:0] undefined
OTP_CTRL_STATUS_LIFE_CYCLE_ERROR_RESVAL logic [0:0] undefined
OTP_CTRL_STATUS_DAI_ERROR_RESVAL logic [0:0] undefined
OTP_CTRL_STATUS_LCI_ERROR_RESVAL logic [0:0] undefined
OTP_CTRL_STATUS_TIMEOUT_ERROR_RESVAL logic [0:0] undefined
OTP_CTRL_STATUS_LFSR_FSM_ERROR_RESVAL logic [0:0] undefined
OTP_CTRL_STATUS_SCRAMBLING_FSM_ERROR_RESVAL logic [0:0] undefined
OTP_CTRL_STATUS_KEY_DERIV_FSM_ERROR_RESVAL logic [0:0] undefined
OTP_CTRL_STATUS_BUS_INTEG_ERROR_RESVAL logic [0:0] undefined
OTP_CTRL_STATUS_DAI_IDLE_RESVAL logic [0:0] undefined
OTP_CTRL_STATUS_CHECK_PENDING_RESVAL logic [0:0] undefined
OTP_CTRL_ERR_CODE_RESVAL logic [29:0] undefined
OTP_CTRL_ERR_CODE_ERR_CODE_0_RESVAL logic [2:0] undefined
OTP_CTRL_ERR_CODE_ERR_CODE_1_RESVAL logic [2:0] undefined
OTP_CTRL_ERR_CODE_ERR_CODE_2_RESVAL logic [2:0] undefined
OTP_CTRL_ERR_CODE_ERR_CODE_3_RESVAL logic [2:0] undefined
OTP_CTRL_ERR_CODE_ERR_CODE_4_RESVAL logic [2:0] undefined
OTP_CTRL_ERR_CODE_ERR_CODE_5_RESVAL logic [2:0] undefined
OTP_CTRL_ERR_CODE_ERR_CODE_6_RESVAL logic [2:0] undefined
OTP_CTRL_ERR_CODE_ERR_CODE_7_RESVAL logic [2:0] undefined
OTP_CTRL_ERR_CODE_ERR_CODE_8_RESVAL logic [2:0] undefined
OTP_CTRL_ERR_CODE_ERR_CODE_9_RESVAL logic [2:0] undefined
OTP_CTRL_DIRECT_ACCESS_REGWEN_RESVAL logic [0:0] undefined
OTP_CTRL_DIRECT_ACCESS_REGWEN_DIRECT_ACCESS_REGWEN_RESVAL logic [0:0] undefined
OTP_CTRL_DIRECT_ACCESS_CMD_RESVAL logic [2:0] undefined
OTP_CTRL_DIRECT_ACCESS_CMD_RD_RESVAL logic [0:0] undefined
OTP_CTRL_DIRECT_ACCESS_CMD_WR_RESVAL logic [0:0] undefined
OTP_CTRL_DIRECT_ACCESS_CMD_DIGEST_RESVAL logic [0:0] undefined
OTP_CTRL_DIRECT_ACCESS_RDATA_0_RESVAL logic [31:0] undefined
OTP_CTRL_DIRECT_ACCESS_RDATA_0_DIRECT_ACCESS_RDATA_0_RESVAL logic [31:0] undefined
OTP_CTRL_DIRECT_ACCESS_RDATA_1_RESVAL logic [31:0] undefined
OTP_CTRL_DIRECT_ACCESS_RDATA_1_DIRECT_ACCESS_RDATA_1_RESVAL logic [31:0] undefined
OTP_CTRL_CHECK_TRIGGER_RESVAL logic [1:0] undefined
OTP_CTRL_CHECK_TRIGGER_INTEGRITY_RESVAL logic [0:0] undefined
OTP_CTRL_CHECK_TRIGGER_CONSISTENCY_RESVAL logic [0:0] undefined
OTP_CTRL_VENDOR_TEST_DIGEST_0_RESVAL logic [31:0] undefined
OTP_CTRL_VENDOR_TEST_DIGEST_0_VENDOR_TEST_DIGEST_0_RESVAL logic [31:0] undefined
OTP_CTRL_VENDOR_TEST_DIGEST_1_RESVAL logic [31:0] undefined
OTP_CTRL_VENDOR_TEST_DIGEST_1_VENDOR_TEST_DIGEST_1_RESVAL logic [31:0] undefined
OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_RESVAL logic [31:0] undefined
OTP_CTRL_CREATOR_SW_CFG_DIGEST_0_CREATOR_SW_CFG_DIGEST_0_RESVAL logic [31:0] undefined
OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_RESVAL logic [31:0] undefined
OTP_CTRL_CREATOR_SW_CFG_DIGEST_1_CREATOR_SW_CFG_DIGEST_1_RESVAL logic [31:0] undefined
OTP_CTRL_OWNER_SW_CFG_DIGEST_0_RESVAL logic [31:0] undefined
OTP_CTRL_OWNER_SW_CFG_DIGEST_0_OWNER_SW_CFG_DIGEST_0_RESVAL logic [31:0] undefined
OTP_CTRL_OWNER_SW_CFG_DIGEST_1_RESVAL logic [31:0] undefined
OTP_CTRL_OWNER_SW_CFG_DIGEST_1_OWNER_SW_CFG_DIGEST_1_RESVAL logic [31:0] undefined
OTP_CTRL_HW_CFG_DIGEST_0_RESVAL logic [31:0] undefined
OTP_CTRL_HW_CFG_DIGEST_0_HW_CFG_DIGEST_0_RESVAL logic [31:0] undefined
OTP_CTRL_HW_CFG_DIGEST_1_RESVAL logic [31:0] undefined
OTP_CTRL_HW_CFG_DIGEST_1_HW_CFG_DIGEST_1_RESVAL logic [31:0] undefined
OTP_CTRL_SECRET0_DIGEST_0_RESVAL logic [31:0] undefined
OTP_CTRL_SECRET0_DIGEST_0_SECRET0_DIGEST_0_RESVAL logic [31:0] undefined
OTP_CTRL_SECRET0_DIGEST_1_RESVAL logic [31:0] undefined
OTP_CTRL_SECRET0_DIGEST_1_SECRET0_DIGEST_1_RESVAL logic [31:0] undefined
OTP_CTRL_SECRET1_DIGEST_0_RESVAL logic [31:0] undefined
OTP_CTRL_SECRET1_DIGEST_0_SECRET1_DIGEST_0_RESVAL logic [31:0] undefined
OTP_CTRL_SECRET1_DIGEST_1_RESVAL logic [31:0] undefined
OTP_CTRL_SECRET1_DIGEST_1_SECRET1_DIGEST_1_RESVAL logic [31:0] undefined
OTP_CTRL_SECRET2_DIGEST_0_RESVAL logic [31:0] undefined
OTP_CTRL_SECRET2_DIGEST_0_SECRET2_DIGEST_0_RESVAL logic [31:0] undefined
OTP_CTRL_SECRET2_DIGEST_1_RESVAL logic [31:0] undefined
OTP_CTRL_SECRET2_DIGEST_1_SECRET2_DIGEST_1_RESVAL logic [31:0] logic [CoreAw-1:0]
OTP_CTRL_SW_CFG_WINDOW_SIZE int unsigned 800
OTP_CTRL_CORE_PERMIT logic [3:0] undefined Register width information to check illegal writes for core interface

Types

Name Type Description
otp_ctrl_reg2hw_intr_state_reg_t struct packed {
struct packed {
logic q;
} otp_operation_done;
struct packed {
logic q;
} otp_error;
}		 ///////////////////////////////////////////// Typedefs for registers for core interface // /////////////////////////////////////////////
otp_ctrl_reg2hw_intr_enable_reg_t struct packed {
struct packed {
logic q;
} otp_operation_done;
struct packed {
logic q;
} otp_error;
}
otp_ctrl_reg2hw_intr_test_reg_t struct packed {
struct packed {
logic q;
logic qe;
} otp_operation_done;
struct packed {
logic q;
logic qe;
} otp_error;
}
otp_ctrl_reg2hw_alert_test_reg_t struct packed {
struct packed {
logic q;
logic qe;
} fatal_macro_error;
struct packed {
logic q;
logic qe;
} fatal_check_error;
struct packed {
logic q;
logic qe;
} fatal_bus_integ_error;
}
otp_ctrl_reg2hw_direct_access_cmd_reg_t struct packed {
struct packed {
logic q;
logic qe;
} rd;
struct packed {
logic q;
logic qe;
} wr;
struct packed {
logic q;
logic qe;
} digest;
}
otp_ctrl_reg2hw_direct_access_address_reg_t struct packed {
logic [10:0] q;
}
otp_ctrl_reg2hw_direct_access_wdata_mreg_t struct packed {
logic [31:0] q;
}
otp_ctrl_reg2hw_check_trigger_reg_t struct packed {
struct packed {
logic q;
logic qe;
} integrity;
struct packed {
logic q;
logic qe;
} consistency;
}
otp_ctrl_reg2hw_check_timeout_reg_t struct packed {
logic [31:0] q;
}
otp_ctrl_reg2hw_integrity_check_period_reg_t struct packed {
logic [31:0] q;
}
otp_ctrl_reg2hw_consistency_check_period_reg_t struct packed {
logic [31:0] q;
}
otp_ctrl_reg2hw_vendor_test_read_lock_reg_t struct packed {
logic q;
}
otp_ctrl_reg2hw_creator_sw_cfg_read_lock_reg_t struct packed {
logic q;
}
otp_ctrl_reg2hw_owner_sw_cfg_read_lock_reg_t struct packed {
logic q;
}
otp_ctrl_hw2reg_intr_state_reg_t struct packed {
struct packed {
logic d;
logic de;
} otp_operation_done;
struct packed {
logic d;
logic de;
} otp_error;
}
otp_ctrl_hw2reg_status_reg_t struct packed {
struct packed {
logic d;
} vendor_test_error;
struct packed {
logic d;
} creator_sw_cfg_error;
struct packed {
logic d;
} owner_sw_cfg_error;
struct packed {
logic d;
} hw_cfg_error;
struct packed {
logic d;
} secret0_error;
struct packed {
logic d;
} secret1_error;
struct packed {
logic d;
} secret2_error;
struct packed {
logic d;
} life_cycle_error;
struct packed {
logic d;
} dai_error;
struct packed {
logic d;
} lci_error;
struct packed {
logic d;
} timeout_error;
struct packed {
logic d;
} lfsr_fsm_error;
struct packed {
logic d;
} scrambling_fsm_error;
struct packed {
logic d;
} key_deriv_fsm_error;
struct packed {
logic d;
} bus_integ_error;
struct packed {
logic d;
} dai_idle;
struct packed {
logic d;
} check_pending;
}
otp_ctrl_hw2reg_err_code_mreg_t struct packed {
logic [2:0] d;
}
otp_ctrl_hw2reg_direct_access_regwen_reg_t struct packed {
logic d;
}
otp_ctrl_hw2reg_direct_access_rdata_mreg_t struct packed {
logic [31:0] d;
}
otp_ctrl_hw2reg_vendor_test_digest_mreg_t struct packed {
logic [31:0] d;
}
otp_ctrl_hw2reg_creator_sw_cfg_digest_mreg_t struct packed {
logic [31:0] d;
}
otp_ctrl_hw2reg_owner_sw_cfg_digest_mreg_t struct packed {
logic [31:0] d;
}
otp_ctrl_hw2reg_hw_cfg_digest_mreg_t struct packed {
logic [31:0] d;
}
otp_ctrl_hw2reg_secret0_digest_mreg_t struct packed {
logic [31:0] d;
}
otp_ctrl_hw2reg_secret1_digest_mreg_t struct packed {
logic [31:0] d;
}
otp_ctrl_hw2reg_secret2_digest_mreg_t struct packed {
logic [31:0] d;
}
otp_ctrl_reg2hw_direct_access_wdata_mreg_t struct packed {
otp_ctrl_reg2hw_intr_state_reg_t intr_state;
otp_ctrl_reg2hw_intr_enable_reg_t intr_enable;
otp_ctrl_reg2hw_intr_test_reg_t intr_test;
otp_ctrl_reg2hw_alert_test_reg_t alert_test;
otp_ctrl_reg2hw_direct_access_cmd_reg_t direct_access_cmd;
otp_ctrl_reg2hw_direct_access_address_reg_t direct_access_address;
otp_ctrl_reg2hw_direct_access_wdata_mreg_t [1:0] direct_access_wdata;
otp_ctrl_reg2hw_check_trigger_reg_t check_trigger;
otp_ctrl_reg2hw_check_timeout_reg_t check_timeout;
otp_ctrl_reg2hw_integrity_check_period_reg_t integrity_check_period;
otp_ctrl_reg2hw_consistency_check_period_reg_t consistency_check_period;
otp_ctrl_reg2hw_vendor_test_read_lock_reg_t vendor_test_read_lock;
otp_ctrl_reg2hw_creator_sw_cfg_read_lock_reg_t creator_sw_cfg_read_lock;
otp_ctrl_reg2hw_owner_sw_cfg_read_lock_reg_t owner_sw_cfg_read_lock;
}		 Register -> HW type for core interface
otp_ctrl_hw2reg_err_code_mreg_t struct packed {
otp_ctrl_hw2reg_intr_state_reg_t intr_state;
otp_ctrl_hw2reg_status_reg_t status;
otp_ctrl_hw2reg_err_code_mreg_t [9:0] err_code;
otp_ctrl_hw2reg_direct_access_regwen_reg_t direct_access_regwen;
otp_ctrl_hw2reg_direct_access_rdata_mreg_t [1:0] direct_access_rdata;
otp_ctrl_hw2reg_vendor_test_digest_mreg_t [1:0] vendor_test_digest;
otp_ctrl_hw2reg_creator_sw_cfg_digest_mreg_t [1:0] creator_sw_cfg_digest;
otp_ctrl_hw2reg_owner_sw_cfg_digest_mreg_t [1:0] owner_sw_cfg_digest;
otp_ctrl_hw2reg_hw_cfg_digest_mreg_t [1:0] hw_cfg_digest;
otp_ctrl_hw2reg_secret0_digest_mreg_t [1:0] secret0_digest;
otp_ctrl_hw2reg_secret1_digest_mreg_t [1:0] secret1_digest;
otp_ctrl_hw2reg_secret2_digest_mreg_t [1:0] secret2_digest;
}		 HW -> register type for core interface
otp_ctrl_core_id_e enum int {
OTP_CTRL_INTR_STATE,
OTP_CTRL_INTR_ENABLE,
OTP_CTRL_INTR_TEST,
OTP_CTRL_ALERT_TEST,
OTP_CTRL_STATUS,
OTP_CTRL_ERR_CODE,
OTP_CTRL_DIRECT_ACCESS_REGWEN,
OTP_CTRL_DIRECT_ACCESS_CMD,
OTP_CTRL_DIRECT_ACCESS_ADDRESS,
OTP_CTRL_DIRECT_ACCESS_WDATA_0,
OTP_CTRL_DIRECT_ACCESS_WDATA_1,
OTP_CTRL_DIRECT_ACCESS_RDATA_0,
OTP_CTRL_DIRECT_ACCESS_RDATA_1,
OTP_CTRL_CHECK_TRIGGER_REGWEN,
OTP_CTRL_CHECK_TRIGGER,
OTP_CTRL_CHECK_REGWEN,
OTP_CTRL_CHECK_TIMEOUT,
OTP_CTRL_INTEGRITY_CHECK_PERIOD,
OTP_CTRL_CONSISTENCY_CHECK_PERIOD,
OTP_CTRL_VENDOR_TEST_READ_LOCK,
OTP_CTRL_CREATOR_SW_CFG_READ_LOCK,
OTP_CTRL_OWNER_SW_CFG_READ_LOCK,
OTP_CTRL_VENDOR_TEST_DIGEST_0,
OTP_CTRL_VENDOR_TEST_DIGEST_1,
OTP_CTRL_CREATOR_SW_CFG_DIGEST_0,
OTP_CTRL_CREATOR_SW_CFG_DIGEST_1,
OTP_CTRL_OWNER_SW_CFG_DIGEST_0,
OTP_CTRL_OWNER_SW_CFG_DIGEST_1,
OTP_CTRL_HW_CFG_DIGEST_0,
OTP_CTRL_HW_CFG_DIGEST_1,
OTP_CTRL_SECRET0_DIGEST_0,
OTP_CTRL_SECRET0_DIGEST_1,
OTP_CTRL_SECRET1_DIGEST_0,
OTP_CTRL_SECRET1_DIGEST_1,
OTP_CTRL_SECRET2_DIGEST_0,
OTP_CTRL_SECRET2_DIGEST_1 }		 Register index for core interface