Package: pattgen_reg_pkg

Description

Copyright lowRISC contributors.
Licensed under the Apache License, Version 2.0, see LICENSE for details.
SPDX-License-Identifier: Apache-2.0

Register Package auto-generated by reggen containing data structure

Constants

Name Type Value Description
NumRegsData int 2
NumAlerts int 1
BlockAw int 6 Address widths within the block
BlockAw logic [BlockAw-1:0] undefined Register offsets
BlockAw logic [BlockAw-1:0] 4
BlockAw logic [BlockAw-1:0] 8
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 10
BlockAw logic [BlockAw-1:0] 14
BlockAw logic [BlockAw-1:0] 18
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 20
BlockAw logic [BlockAw-1:0] 24
BlockAw logic [BlockAw-1:0] 28
BlockAw logic [BlockAw-1:0] c
PATTGEN_INTR_TEST_RESVAL logic [1:0] undefined Reset values for hwext registers and their fields
PATTGEN_INTR_TEST_DONE_CH0_RESVAL logic [0:0] undefined
PATTGEN_INTR_TEST_DONE_CH1_RESVAL logic [0:0] undefined
PATTGEN_ALERT_TEST_RESVAL logic [0:0] undefined
PATTGEN_ALERT_TEST_FATAL_FAULT_RESVAL logic [0:0]
PATTGEN_PERMIT logic [3:0] undefined Register width information to check illegal writes

Types

Name Type Description
pattgen_reg2hw_intr_state_reg_t struct packed {
struct packed {
logic q;
} done_ch0;
struct packed {
logic q;
} done_ch1;
}		 ////////////////////////// Typedefs for registers // //////////////////////////
pattgen_reg2hw_intr_enable_reg_t struct packed {
struct packed {
logic q;
} done_ch0;
struct packed {
logic q;
} done_ch1;
}
pattgen_reg2hw_intr_test_reg_t struct packed {
struct packed {
logic q;
logic qe;
} done_ch0;
struct packed {
logic q;
logic qe;
} done_ch1;
}
pattgen_reg2hw_alert_test_reg_t struct packed {
logic q;
logic qe;
}
pattgen_reg2hw_ctrl_reg_t struct packed {
struct packed {
logic q;
} enable_ch0;
struct packed {
logic q;
} enable_ch1;
struct packed {
logic q;
} polarity_ch0;
struct packed {
logic q;
} polarity_ch1;
}
pattgen_reg2hw_prediv_ch0_reg_t struct packed {
logic [31:0] q;
}
pattgen_reg2hw_prediv_ch1_reg_t struct packed {
logic [31:0] q;
}
pattgen_reg2hw_data_ch0_mreg_t struct packed {
logic [31:0] q;
}
pattgen_reg2hw_data_ch1_mreg_t struct packed {
logic [31:0] q;
}
pattgen_reg2hw_size_reg_t struct packed {
struct packed {
logic [5:0] q;
} len_ch0;
struct packed {
logic [9:0] q;
} reps_ch0;
struct packed {
logic [5:0] q;
} len_ch1;
struct packed {
logic [9:0] q;
} reps_ch1;
}
pattgen_hw2reg_intr_state_reg_t struct packed {
struct packed {
logic d;
logic de;
} done_ch0;
struct packed {
logic d;
logic de;
} done_ch1;
}
pattgen_reg2hw_data_ch0_mreg_t struct packed {
pattgen_reg2hw_intr_state_reg_t intr_state;
pattgen_reg2hw_intr_enable_reg_t intr_enable;
pattgen_reg2hw_intr_test_reg_t intr_test;
pattgen_reg2hw_alert_test_reg_t alert_test;
pattgen_reg2hw_ctrl_reg_t ctrl;
pattgen_reg2hw_prediv_ch0_reg_t prediv_ch0;
pattgen_reg2hw_prediv_ch1_reg_t prediv_ch1;
pattgen_reg2hw_data_ch0_mreg_t [1:0] data_ch0;
pattgen_reg2hw_data_ch1_mreg_t [1:0] data_ch1;
pattgen_reg2hw_size_reg_t size;
}		 Register -> HW type
pattgen_hw2reg_t struct packed {
pattgen_hw2reg_intr_state_reg_t intr_state;
}		 HW -> register type