Entity: pattgen_reg_top
- File: pattgen_reg_top.sv
Diagram
Description
Copyright lowRISC contributors. Licensed under the Apache License, Version 2.0, see LICENSE for details. SPDX-License-Identifier: Apache-2.0
Register Top module auto-generated by reggen
Ports
| Port name | Direction | Type | Description |
|---|---|---|---|
| clk_i | input | ||
| rst_ni | input | ||
| tl_i | input | ||
| tl_o | output | ||
| reg2hw | output | Write | |
| hw2reg | input | Read | |
| intg_err_o | output | Integrity check errors | |
| devmode_i | input | If 1, explicit error return for unmapped register access |
Signals
| Name | Type | Description |
|---|---|---|
| reg_we | logic | register signals |
| reg_re | logic | |
| reg_addr | logic [AW-1:0] | |
| reg_wdata | logic [DW-1:0] | |
| reg_be | logic [DBW-1:0] | |
| reg_rdata | logic [DW-1:0] | |
| reg_error | logic | |
| addrmiss | logic | |
| wr_err | logic | |
| reg_rdata_next | logic [DW-1:0] | |
| reg_busy | logic | |
| tl_reg_h2d | tlul_pkg::tl_h2d_t | |
| tl_reg_d2h | tlul_pkg::tl_d2h_t | |
| intg_err | logic | incoming payload check |
| intg_err_q | logic | |
| tl_o_pre | tlul_pkg::tl_d2h_t | outgoing integrity generation |
| intr_state_we | logic | Define SW related signals Format: |
| intr_state_done_ch0_qs | logic | |
| intr_state_done_ch0_wd | logic | |
| intr_state_done_ch1_qs | logic | |
| intr_state_done_ch1_wd | logic | |
| intr_enable_we | logic | |
| intr_enable_done_ch0_qs | logic | |
| intr_enable_done_ch0_wd | logic | |
| intr_enable_done_ch1_qs | logic | |
| intr_enable_done_ch1_wd | logic | |
| intr_test_we | logic | |
| intr_test_done_ch0_wd | logic | |
| intr_test_done_ch1_wd | logic | |
| alert_test_we | logic | |
| alert_test_wd | logic | |
| ctrl_we | logic | |
| ctrl_enable_ch0_qs | logic | |
| ctrl_enable_ch0_wd | logic | |
| ctrl_enable_ch1_qs | logic | |
| ctrl_enable_ch1_wd | logic | |
| ctrl_polarity_ch0_qs | logic | |
| ctrl_polarity_ch0_wd | logic | |
| ctrl_polarity_ch1_qs | logic | |
| ctrl_polarity_ch1_wd | logic | |
| prediv_ch0_we | logic | |
| prediv_ch0_qs | logic [31:0] | |
| prediv_ch0_wd | logic [31:0] | |
| prediv_ch1_we | logic | |
| prediv_ch1_qs | logic [31:0] | |
| prediv_ch1_wd | logic [31:0] | |
| data_ch0_0_we | logic | |
| data_ch0_0_qs | logic [31:0] | |
| data_ch0_0_wd | logic [31:0] | |
| data_ch0_1_we | logic | |
| data_ch0_1_qs | logic [31:0] | |
| data_ch0_1_wd | logic [31:0] | |
| data_ch1_0_we | logic | |
| data_ch1_0_qs | logic [31:0] | |
| data_ch1_0_wd | logic [31:0] | |
| data_ch1_1_we | logic | |
| data_ch1_1_qs | logic [31:0] | |
| data_ch1_1_wd | logic [31:0] | |
| size_we | logic | |
| size_len_ch0_qs | logic [5:0] | |
| size_len_ch0_wd | logic [5:0] | |
| size_reps_ch0_qs | logic [9:0] | |
| size_reps_ch0_wd | logic [9:0] | |
| size_len_ch1_qs | logic [5:0] | |
| size_len_ch1_wd | logic [5:0] | |
| size_reps_ch1_qs | logic [9:0] | |
| size_reps_ch1_wd | logic [9:0] | |
| addr_hit | logic [11:0] | |
| shadow_busy | logic | shadow busy |
| reg_busy_sel | logic | register busy |
| unused_wdata | logic | Unused signal tieoff wdata / byte enable are not always fully used add a blanket unused statement to handle lint waivers |
| unused_be | logic |
Constants
| Name | Type | Value | Description |
|---|---|---|---|
| AW | int | 6 | |
| DW | int | 32 | |
| DBW | int | DW/8 | Byte Width |
Processes
- unnamed: ( @(posedge clk_i or negedge rst_ni) )
Type: always_ff
- unnamed: ( )
Type: always_comb
- unnamed: ( )
Type: always_comb
Description
Check sub-word write is permitted
- unnamed: ( )
Type: always_comb
Description
Read data return
- unnamed: ( )
Type: always_comb
Instantiations
- u_chk: tlul_cmd_intg_chk
- u_rsp_intg_gen: tlul_rsp_intg_gen
- u_reg_if: tlul_adapter_reg
- u_intr_state_done_ch0: prim_subreg
Description
Register instances
R[intr_state]: V(False)
F[done_ch0]: 0:0
- u_intr_state_done_ch1: prim_subreg
Description
F[done_ch1]: 1:1
- u_intr_enable_done_ch0: prim_subreg
Description
R[intr_enable]: V(False)
F[done_ch0]: 0:0
- u_intr_enable_done_ch1: prim_subreg
Description
F[done_ch1]: 1:1
- u_intr_test_done_ch0: prim_subreg_ext
Description
R[intr_test]: V(True)
F[done_ch0]: 0:0
- u_intr_test_done_ch1: prim_subreg_ext
Description
F[done_ch1]: 1:1
- u_alert_test: prim_subreg_ext
Description
R[alert_test]: V(True)
- u_ctrl_enable_ch0: prim_subreg
Description
R[ctrl]: V(False)
F[enable_ch0]: 0:0
- u_ctrl_enable_ch1: prim_subreg
Description
F[enable_ch1]: 1:1
- u_ctrl_polarity_ch0: prim_subreg
Description
F[polarity_ch0]: 2:2
- u_ctrl_polarity_ch1: prim_subreg
Description
F[polarity_ch1]: 3:3
- u_prediv_ch0: prim_subreg
Description
R[prediv_ch0]: V(False)
- u_prediv_ch1: prim_subreg
Description
R[prediv_ch1]: V(False)
- u_size_len_ch0: prim_subreg
Description
R[size]: V(False)
F[len_ch0]: 5:0
- u_size_reps_ch0: prim_subreg
Description
F[reps_ch0]: 15:6
- u_size_len_ch1: prim_subreg
Description
F[len_ch1]: 21:16
- u_size_reps_ch1: prim_subreg
Description
F[reps_ch1]: 31:22