Entity: prim_packer_fifo

Diagram

int InW int OutW int MaxW int MinW int DepthW clk_i rst_ni clr_i wvalid_i [InW-1:0] wdata_i rready_i wready_o rvalid_o [OutW-1:0] rdata_o [DepthW:0] depth_o

Description

Copyright lowRISC contributors. Licensed under the Apache License, Version 2.0, see LICENSE for details. SPDX-License-Identifier: Apache-2.0

Supports packed and unpacked modes Uses FIFO timing on the control signals No masking or flush functions supported Timings - case where InW < OutW clk_i ||||||||||||||||| wvalid_i ||||||||_______ wdata_i Val N |Val N+1 |Val N+2 |Val N+3 |------------------- wready_o ~~~~~~~~~|_|~~ rvalid_o __________________________________|~~| rdata_o -------------------------------------------|Val |-------- rready_i _______________________________________|| depth_o 0000000000|1111111111|2222222222|3333333333|4444444444|00000000 Timings - case where InW > OutW clk_i |||||||||||||||||_ wvalid_i |~~|______________________________________________ wdata_i -----|Val |---------------------------------------------------- wready_o ~~|_______________________________|~~ rvalid_o _|~~~~~~~~~| rdata_o ----------|Val N |Val N+1 |Val N+2 |Val N+3 |-------- rready_i _____||||||||_ depth_o 0000000000|4444444444|3333333333|2222222222|1111111111|00000000 Timings - case where InW = OutW clk_i ||||||||||||||||| wvalid_i |~~|_____________________________________________ wdata_i -----|Val |---------------------------------------------------- wready_o ~~|_|~~~~~~~~~ rvalid_o _|~~|_____________________________ rdata_o ----------|Val |----------------------------------------- rready_i ____|~~|_____________________________ depth_o 0000000000|1111111111|00000000000000000000000000000000000000000

Generics

Generic name Type Value Description
InW int 32
OutW int 8
MaxW int InW derived parameters
MinW int InW
DepthW int $clog2(MaxW/MinW)

Ports

Port name Direction Type Description
clk_i input
rst_ni input
clr_i input
wvalid_i input
wdata_i input [InW-1:0]
wready_o output
rvalid_o output
rdata_o output [OutW-1:0]
rready_i input
depth_o output [DepthW:0]

Signals

Name Type Description
load_data logic signals
clear_data logic
depth_q logic [DepthW:0] flops
depth_d logic [DepthW:0] flops
data_q logic [MaxW-1:0]
data_d logic [MaxW-1:0]
clr_q logic
clr_d logic

Constants

Name Type Value Description
MaxW int InW derived parameters
MinW int InW
DepthW int $clog2(MaxW/MinW)
WidthRatio int unsigned MaxW / MinW
FullDepth bit [DepthW:0] WidthRatio[DepthW:0]

Processes

Type: always_ff