Entity: pwrmgr_cdc

Diagram

clk_slow_i clk_i rst_slow_ni rst_ni slow_req_pwrup_i slow_ack_pwrdn_i slow_pwrup_cause_toggle_i pwrup_cause_e slow_pwrup_cause_i pwr_peri_t slow_peri_reqs_masked_i req_pwrdn_i ack_pwrup_i cfg_cdc_sync_i [NumWkups-1:0] wakeup_en_i [NumRstReqs-1:0] reset_en_i main_pd_ni io_clk_en_i core_clk_en_i usb_clk_en_lp_i usb_clk_en_active_i pwr_peri_t peri_i pwr_flash_t flash_i pwr_otp_rsp_t otp_i pwr_ast_rsp_t ast_i rom_ctrl_done_i [NumWkups-1:0] slow_wakeup_en_o [NumRstReqs-1:0] slow_reset_en_o slow_main_pd_no slow_io_clk_en_o slow_core_clk_en_o slow_usb_clk_en_lp_o slow_usb_clk_en_active_o slow_req_pwrdn_o slow_ack_pwrup_o pwr_ast_rsp_t slow_ast_o pwr_peri_t slow_peri_reqs_o ack_pwrdn_o req_pwrup_o pwrup_cause_e pwrup_cause_o pwr_peri_t peri_reqs_o cdc_sync_done_o pwr_flash_t flash_o pwr_otp_rsp_t otp_o rom_ctrl_done_o

Description

Copyright lowRISC contributors. Licensed under the Apache License, Version 2.0, see LICENSE for details. SPDX-License-Identifier: Apache-2.0

Power Manager CDC handling

Ports

Port name Direction Type Description
clk_slow_i input Clocks and resets
clk_i input
rst_slow_ni input
rst_ni input
slow_req_pwrup_i input slow domain signals,
slow_ack_pwrdn_i input
slow_pwrup_cause_toggle_i input
slow_pwrup_cause_i input pwrup_cause_e
slow_wakeup_en_o output [NumWkups-1:0]
slow_reset_en_o output [NumRstReqs-1:0]
slow_main_pd_no output
slow_io_clk_en_o output
slow_core_clk_en_o output
slow_usb_clk_en_lp_o output
slow_usb_clk_en_active_o output
slow_req_pwrdn_o output
slow_ack_pwrup_o output
slow_ast_o output pwr_ast_rsp_t
slow_peri_reqs_o output pwr_peri_t
slow_peri_reqs_masked_i input pwr_peri_t
req_pwrdn_i input fast domain signals
ack_pwrup_i input
cfg_cdc_sync_i input
wakeup_en_i input [NumWkups-1:0]
reset_en_i input [NumRstReqs-1:0]
main_pd_ni input
io_clk_en_i input
core_clk_en_i input
usb_clk_en_lp_i input
usb_clk_en_active_i input
ack_pwrdn_o output
req_pwrup_o output
pwrup_cause_o output pwrup_cause_e
peri_reqs_o output pwr_peri_t
cdc_sync_done_o output
peri_i input pwr_peri_t peripheral inputs, mixed domains
flash_i input pwr_flash_t
flash_o output pwr_flash_t
otp_i input pwr_otp_rsp_t otp interface
otp_o output pwr_otp_rsp_t
ast_i input pwr_ast_rsp_t AST inputs, unknown domain
rom_ctrl_done_i input rom_ctrl signals
rom_ctrl_done_o output

Signals

Name Type Description
slow_cdc_sync logic ////////////////////////////// Sync from clk_i to clk_slow_i //////////////////////////////
slow_ast_q pwr_ast_rsp_t
slow_ast_q2 pwr_ast_rsp_t
pwrup_cause_toggle_q logic ////////////////////////////// Sync from clk_slow_i to clk_i //////////////////////////////
pwrup_cause_toggle_q2 logic ////////////////////////////// Sync from clk_slow_i to clk_i //////////////////////////////
pwrup_cause_chg logic

Processes

Type: always_ff

Type: always_ff

Description
if possible, we should simulate below with random delays through flop_2sync

Type: always_ff

Description
only register configurations can be sync'd using slow_cdc_sync

Type: always_ff

Type: always_ff

Instantiations