Entity: pwrmgr_reg_top

File: pwrmgr_reg_top.sv

Diagram

Description

Copyright lowRISC contributors. Licensed under the Apache License, Version 2.0, see LICENSE for details. SPDX-License-Identifier: Apache-2.0

Ports

Port name	Direction	Description
clk_i	input
rst_ni	input
tl_i	input
tl_o	output
reg2hw	output	Write
hw2reg	input	Read
intg_err_o	output	Integrity check errors
devmode_i	input	If 1, explicit error return for unmapped register access

Signals

Name	Type	Description
reg_we	logic	register signals
reg_re	logic
reg_addr	logic [AW-1:0]
reg_wdata	logic [DW-1:0]
reg_be	logic [DBW-1:0]
reg_rdata	logic [DW-1:0]
reg_error	logic
addrmiss	logic
wr_err	logic
reg_rdata_next	logic [DW-1:0]
reg_busy	logic
tl_reg_h2d	tlul_pkg::tl_h2d_t
tl_reg_d2h	tlul_pkg::tl_d2h_t
intg_err	logic	incoming payload check
intg_err_q	logic
tl_o_pre	tlul_pkg::tl_d2h_t	outgoing integrity generation
intr_state_we	logic	Define SW related signals Format: {wd
intr_state_qs	logic
intr_state_wd	logic
intr_enable_we	logic
intr_enable_qs	logic
intr_enable_wd	logic
intr_test_we	logic
intr_test_wd	logic
ctrl_cfg_regwen_re	logic
ctrl_cfg_regwen_qs	logic
control_we	logic
control_low_power_hint_qs	logic
control_low_power_hint_wd	logic
control_core_clk_en_qs	logic
control_core_clk_en_wd	logic
control_io_clk_en_qs	logic
control_io_clk_en_wd	logic
control_usb_clk_en_lp_qs	logic
control_usb_clk_en_lp_wd	logic
control_usb_clk_en_active_qs	logic
control_usb_clk_en_active_wd	logic
control_main_pd_n_qs	logic
control_main_pd_n_wd	logic
cfg_cdc_sync_we	logic
cfg_cdc_sync_qs	logic
cfg_cdc_sync_wd	logic
wakeup_en_regwen_we	logic
wakeup_en_regwen_qs	logic
wakeup_en_regwen_wd	logic
wakeup_en_we	logic
wakeup_en_qs	logic
wakeup_en_wd	logic
wake_status_qs	logic
reset_en_regwen_we	logic
reset_en_regwen_qs	logic
reset_en_regwen_wd	logic
reset_en_we	logic
reset_en_qs	logic
reset_en_wd	logic
reset_status_qs	logic
wake_info_capture_dis_we	logic
wake_info_capture_dis_qs	logic
wake_info_capture_dis_wd	logic
wake_info_re	logic
wake_info_we	logic
wake_info_reasons_qs	logic
wake_info_reasons_wd	logic
wake_info_fall_through_qs	logic
wake_info_fall_through_wd	logic
wake_info_abort_qs	logic
wake_info_abort_wd	logic
addr_hit	logic [13:0]
shadow_busy	logic	shadow busy
reg_busy_sel	logic	register busy
unused_wdata	logic	Unused signal tieoff wdata / byte enable are not always fully used add a blanket unused statement to handle lint waivers
unused_be	logic

Constants

Name	Type	Value	Description
AW	int	6
DW	int	32
DBW	int	DW/8	Byte Width

Processes

unnamed: ( @(posedge clk_i or negedge rst_ni) )

Type: always_ff

unnamed: ( )

Type: always_comb

unnamed: ( )

Type: always_comb

Description
Check sub-word write is permitted

unnamed: ( )

Type: always_comb

Description
Read data return

unnamed: ( )

Type: always_comb

Instantiations

u_chk: tlul_cmd_intg_chk

u_rsp_intg_gen: tlul_rsp_intg_gen

u_reg_if: tlul_adapter_reg

u_intr_state: prim_subreg

Description
Register instances
R[intr_state]: V(False)

u_intr_enable: prim_subreg

Description
R[intr_enable]: V(False)

u_intr_test: prim_subreg_ext

Description
R[intr_test]: V(True)

u_ctrl_cfg_regwen: prim_subreg_ext

Description
R[ctrl_cfg_regwen]: V(True)

u_control_low_power_hint: prim_subreg

Description
R[control]: V(False)
F[low_power_hint]: 0:0

u_control_core_clk_en: prim_subreg

Description
F[core_clk_en]: 4:4

u_control_io_clk_en: prim_subreg

Description
F[io_clk_en]: 5:5

u_control_usb_clk_en_lp: prim_subreg

Description
F[usb_clk_en_lp]: 6:6

u_control_usb_clk_en_active: prim_subreg

Description
F[usb_clk_en_active]: 7:7

u_control_main_pd_n: prim_subreg

Description
F[main_pd_n]: 8:8

u_cfg_cdc_sync: prim_subreg

Description
R[cfg_cdc_sync]: V(False)

u_wakeup_en_regwen: prim_subreg

Description
R[wakeup_en_regwen]: V(False)

u_reset_en_regwen: prim_subreg

Description
R[reset_en_regwen]: V(False)

u_wake_info_capture_dis: prim_subreg

Description
R[wake_info_capture_dis]: V(False)

u_wake_info_reasons: prim_subreg_ext

Description
R[wake_info]: V(True)
F[reasons]: 0:0

u_wake_info_fall_through: prim_subreg_ext

Description
F[fall_through]: 1:1

u_wake_info_abort: prim_subreg_ext

Description
F[abort]: 2:2