Entity: rv_core_ibex_cfg_reg_top

File: rv_core_ibex_cfg_reg_top.sv

Diagram

Description

Copyright lowRISC contributors. Licensed under the Apache License, Version 2.0, see LICENSE for details. SPDX-License-Identifier: Apache-2.0

Ports

Port name	Direction	Description
clk_i	input
rst_ni	input
tl_i	input
tl_o	output
reg2hw	output	Write
hw2reg	input	Read
intg_err_o	output	Integrity check errors
devmode_i	input	If 1, explicit error return for unmapped register access

Signals

Name	Type	Description
reg_we	logic	register signals
reg_re	logic
reg_addr	logic [AW-1:0]
reg_wdata	logic [DW-1:0]
reg_be	logic [DBW-1:0]
reg_rdata	logic [DW-1:0]
reg_error	logic
addrmiss	logic
wr_err	logic
reg_rdata_next	logic [DW-1:0]
reg_busy	logic
tl_reg_h2d	tlul_pkg::tl_h2d_t
tl_reg_d2h	tlul_pkg::tl_d2h_t
intg_err	logic	incoming payload check
intg_err_q	logic
tl_o_pre	tlul_pkg::tl_d2h_t	outgoing integrity generation
alert_test_we	logic	Define SW related signals Format: {wd
alert_test_fatal_sw_err_wd	logic
alert_test_recov_sw_err_wd	logic
alert_test_fatal_hw_err_wd	logic
alert_test_recov_hw_err_wd	logic
sw_alert_regwen_0_we	logic
sw_alert_regwen_0_qs	logic
sw_alert_regwen_0_wd	logic
sw_alert_regwen_1_we	logic
sw_alert_regwen_1_qs	logic
sw_alert_regwen_1_wd	logic
sw_alert_0_we	logic
sw_alert_0_qs	logic [1:0]
sw_alert_0_wd	logic [1:0]
sw_alert_1_we	logic
sw_alert_1_qs	logic [1:0]
sw_alert_1_wd	logic [1:0]
ibus_regwen_0_we	logic
ibus_regwen_0_qs	logic
ibus_regwen_0_wd	logic
ibus_regwen_1_we	logic
ibus_regwen_1_qs	logic
ibus_regwen_1_wd	logic
ibus_addr_en_0_we	logic
ibus_addr_en_0_qs	logic
ibus_addr_en_0_wd	logic
ibus_addr_en_1_we	logic
ibus_addr_en_1_qs	logic
ibus_addr_en_1_wd	logic
ibus_addr_matching_0_we	logic
ibus_addr_matching_0_qs	logic [31:0]
ibus_addr_matching_0_wd	logic [31:0]
ibus_addr_matching_1_we	logic
ibus_addr_matching_1_qs	logic [31:0]
ibus_addr_matching_1_wd	logic [31:0]
ibus_remap_addr_0_we	logic
ibus_remap_addr_0_qs	logic [31:0]
ibus_remap_addr_0_wd	logic [31:0]
ibus_remap_addr_1_we	logic
ibus_remap_addr_1_qs	logic [31:0]
ibus_remap_addr_1_wd	logic [31:0]
dbus_regwen_0_we	logic
dbus_regwen_0_qs	logic
dbus_regwen_0_wd	logic
dbus_regwen_1_we	logic
dbus_regwen_1_qs	logic
dbus_regwen_1_wd	logic
dbus_addr_en_0_we	logic
dbus_addr_en_0_qs	logic
dbus_addr_en_0_wd	logic
dbus_addr_en_1_we	logic
dbus_addr_en_1_qs	logic
dbus_addr_en_1_wd	logic
dbus_addr_matching_0_we	logic
dbus_addr_matching_0_qs	logic [31:0]
dbus_addr_matching_0_wd	logic [31:0]
dbus_addr_matching_1_we	logic
dbus_addr_matching_1_qs	logic [31:0]
dbus_addr_matching_1_wd	logic [31:0]
dbus_remap_addr_0_we	logic
dbus_remap_addr_0_qs	logic [31:0]
dbus_remap_addr_0_wd	logic [31:0]
dbus_remap_addr_1_we	logic
dbus_remap_addr_1_qs	logic [31:0]
dbus_remap_addr_1_wd	logic [31:0]
nmi_enable_we	logic
nmi_enable_alert_en_qs	logic
nmi_enable_alert_en_wd	logic
nmi_enable_wdog_en_qs	logic
nmi_enable_wdog_en_wd	logic
nmi_state_we	logic
nmi_state_alert_qs	logic
nmi_state_alert_wd	logic
nmi_state_wdog_qs	logic
nmi_state_wdog_wd	logic
err_status_we	logic
err_status_reg_intg_err_qs	logic
err_status_reg_intg_err_wd	logic
err_status_fatal_intg_err_qs	logic
err_status_fatal_intg_err_wd	logic
err_status_fatal_core_err_qs	logic
err_status_fatal_core_err_wd	logic
err_status_recov_core_err_qs	logic
err_status_recov_core_err_wd	logic
addr_hit	logic [23:0]
shadow_busy	logic	shadow busy
reg_busy_sel	logic	register busy
unused_wdata	logic	Unused signal tieoff wdata / byte enable are not always fully used add a blanket unused statement to handle lint waivers
unused_be	logic

Constants

Name	Type	Value	Description
AW	int	7
DW	int	32
DBW	int	DW/8	Byte Width

Processes

unnamed: ( @(posedge clk_i or negedge rst_ni) )

Type: always_ff

unnamed: ( )

Type: always_comb

unnamed: ( )

Type: always_comb

Description
Check sub-word write is permitted

unnamed: ( )

Type: always_comb

Description
Read data return

unnamed: ( )

Type: always_comb

Instantiations

u_chk: tlul_cmd_intg_chk

u_rsp_intg_gen: tlul_rsp_intg_gen

u_reg_if: tlul_adapter_reg

u_alert_test_fatal_sw_err: prim_subreg_ext

Description
Register instances
R[alert_test]: V(True)
F[fatal_sw_err]: 0:0

u_alert_test_recov_sw_err: prim_subreg_ext

Description
F[recov_sw_err]: 1:1

u_alert_test_fatal_hw_err: prim_subreg_ext

Description
F[fatal_hw_err]: 2:2

u_alert_test_recov_hw_err: prim_subreg_ext

Description
F[recov_hw_err]: 3:3

u_sw_alert_regwen_0: prim_subreg

Description
Subregister 0 of Multireg sw_alert_regwen
R[sw_alert_regwen_0]: V(False)

u_sw_alert_regwen_1: prim_subreg

Description
Subregister 1 of Multireg sw_alert_regwen
R[sw_alert_regwen_1]: V(False)

u_ibus_regwen_0: prim_subreg

Description
Subregister 0 of Multireg ibus_regwen
R[ibus_regwen_0]: V(False)

u_ibus_regwen_1: prim_subreg

Description
Subregister 1 of Multireg ibus_regwen
R[ibus_regwen_1]: V(False)

u_dbus_regwen_0: prim_subreg

Description
Subregister 0 of Multireg dbus_regwen
R[dbus_regwen_0]: V(False)

u_dbus_regwen_1: prim_subreg

Description
Subregister 1 of Multireg dbus_regwen
R[dbus_regwen_1]: V(False)

u_nmi_enable_alert_en: prim_subreg

Description
R[nmi_enable]: V(False)
F[alert_en]: 0:0

u_nmi_enable_wdog_en: prim_subreg

Description
F[wdog_en]: 1:1

u_nmi_state_alert: prim_subreg

Description
R[nmi_state]: V(False)
F[alert]: 0:0

u_nmi_state_wdog: prim_subreg

Description
F[wdog]: 1:1

u_err_status_reg_intg_err: prim_subreg

Description
R[err_status]: V(False)
F[reg_intg_err]: 0:0

u_err_status_fatal_intg_err: prim_subreg

Description
F[fatal_intg_err]: 8:8

u_err_status_fatal_core_err: prim_subreg

Description
F[fatal_core_err]: 9:9

u_err_status_recov_core_err: prim_subreg

Description
F[recov_core_err]: 10:10