Entity: rv_plic_reg_top
- File: rv_plic_reg_top.sv
Diagram
Description
Copyright lowRISC contributors. Licensed under the Apache License, Version 2.0, see LICENSE for details. SPDX-License-Identifier: Apache-2.0
Register Top module auto-generated by reggen
Ports
| Port name | Direction | Type | Description |
|---|---|---|---|
| clk_i | input | ||
| rst_ni | input | ||
| tl_i | input | ||
| tl_o | output | ||
| reg2hw | output | Write | |
| hw2reg | input | Read | |
| intg_err_o | output | Integrity check errors | |
| devmode_i | input | If 1, explicit error return for unmapped register access |
Signals
| Name | Type | Description |
|---|---|---|
| reg_we | logic | register signals |
| reg_re | logic | |
| reg_addr | logic [AW-1:0] | |
| reg_wdata | logic [DW-1:0] | |
| reg_be | logic [DBW-1:0] | |
| reg_rdata | logic [DW-1:0] | |
| reg_error | logic | |
| addrmiss | logic | |
| wr_err | logic | |
| reg_rdata_next | logic [DW-1:0] | |
| reg_busy | logic | |
| tl_reg_h2d | tlul_pkg::tl_h2d_t | |
| tl_reg_d2h | tlul_pkg::tl_d2h_t | |
| intg_err | logic | incoming payload check |
| intg_err_q | logic | |
| tl_o_pre | tlul_pkg::tl_d2h_t | outgoing integrity generation |
| ip_p_0_qs | logic | Define SW related signals Format: |
| ip_p_1_qs | logic | |
| ip_p_2_qs | logic | |
| ip_p_3_qs | logic | |
| ip_p_4_qs | logic | |
| ip_p_5_qs | logic | |
| ip_p_6_qs | logic | |
| ip_p_7_qs | logic | |
| ip_p_8_qs | logic | |
| ip_p_9_qs | logic | |
| ip_p_10_qs | logic | |
| ip_p_11_qs | logic | |
| ip_p_12_qs | logic | |
| ip_p_13_qs | logic | |
| ip_p_14_qs | logic | |
| ip_p_15_qs | logic | |
| ip_p_16_qs | logic | |
| ip_p_17_qs | logic | |
| ip_p_18_qs | logic | |
| ip_p_19_qs | logic | |
| ip_p_20_qs | logic | |
| ip_p_21_qs | logic | |
| ip_p_22_qs | logic | |
| ip_p_23_qs | logic | |
| ip_p_24_qs | logic | |
| ip_p_25_qs | logic | |
| ip_p_26_qs | logic | |
| ip_p_27_qs | logic | |
| ip_p_28_qs | logic | |
| ip_p_29_qs | logic | |
| ip_p_30_qs | logic | |
| ip_p_31_qs | logic | |
| le_we | logic | |
| le_le_0_qs | logic | |
| le_le_0_wd | logic | |
| le_le_1_qs | logic | |
| le_le_1_wd | logic | |
| le_le_2_qs | logic | |
| le_le_2_wd | logic | |
| le_le_3_qs | logic | |
| le_le_3_wd | logic | |
| le_le_4_qs | logic | |
| le_le_4_wd | logic | |
| le_le_5_qs | logic | |
| le_le_5_wd | logic | |
| le_le_6_qs | logic | |
| le_le_6_wd | logic | |
| le_le_7_qs | logic | |
| le_le_7_wd | logic | |
| le_le_8_qs | logic | |
| le_le_8_wd | logic | |
| le_le_9_qs | logic | |
| le_le_9_wd | logic | |
| le_le_10_qs | logic | |
| le_le_10_wd | logic | |
| le_le_11_qs | logic | |
| le_le_11_wd | logic | |
| le_le_12_qs | logic | |
| le_le_12_wd | logic | |
| le_le_13_qs | logic | |
| le_le_13_wd | logic | |
| le_le_14_qs | logic | |
| le_le_14_wd | logic | |
| le_le_15_qs | logic | |
| le_le_15_wd | logic | |
| le_le_16_qs | logic | |
| le_le_16_wd | logic | |
| le_le_17_qs | logic | |
| le_le_17_wd | logic | |
| le_le_18_qs | logic | |
| le_le_18_wd | logic | |
| le_le_19_qs | logic | |
| le_le_19_wd | logic | |
| le_le_20_qs | logic | |
| le_le_20_wd | logic | |
| le_le_21_qs | logic | |
| le_le_21_wd | logic | |
| le_le_22_qs | logic | |
| le_le_22_wd | logic | |
| le_le_23_qs | logic | |
| le_le_23_wd | logic | |
| le_le_24_qs | logic | |
| le_le_24_wd | logic | |
| le_le_25_qs | logic | |
| le_le_25_wd | logic | |
| le_le_26_qs | logic | |
| le_le_26_wd | logic | |
| le_le_27_qs | logic | |
| le_le_27_wd | logic | |
| le_le_28_qs | logic | |
| le_le_28_wd | logic | |
| le_le_29_qs | logic | |
| le_le_29_wd | logic | |
| le_le_30_qs | logic | |
| le_le_30_wd | logic | |
| le_le_31_qs | logic | |
| le_le_31_wd | logic | |
| prio0_we | logic | |
| prio0_qs | logic [2:0] | |
| prio0_wd | logic [2:0] | |
| prio1_we | logic | |
| prio1_qs | logic [2:0] | |
| prio1_wd | logic [2:0] | |
| prio2_we | logic | |
| prio2_qs | logic [2:0] | |
| prio2_wd | logic [2:0] | |
| prio3_we | logic | |
| prio3_qs | logic [2:0] | |
| prio3_wd | logic [2:0] | |
| prio4_we | logic | |
| prio4_qs | logic [2:0] | |
| prio4_wd | logic [2:0] | |
| prio5_we | logic | |
| prio5_qs | logic [2:0] | |
| prio5_wd | logic [2:0] | |
| prio6_we | logic | |
| prio6_qs | logic [2:0] | |
| prio6_wd | logic [2:0] | |
| prio7_we | logic | |
| prio7_qs | logic [2:0] | |
| prio7_wd | logic [2:0] | |
| prio8_we | logic | |
| prio8_qs | logic [2:0] | |
| prio8_wd | logic [2:0] | |
| prio9_we | logic | |
| prio9_qs | logic [2:0] | |
| prio9_wd | logic [2:0] | |
| prio10_we | logic | |
| prio10_qs | logic [2:0] | |
| prio10_wd | logic [2:0] | |
| prio11_we | logic | |
| prio11_qs | logic [2:0] | |
| prio11_wd | logic [2:0] | |
| prio12_we | logic | |
| prio12_qs | logic [2:0] | |
| prio12_wd | logic [2:0] | |
| prio13_we | logic | |
| prio13_qs | logic [2:0] | |
| prio13_wd | logic [2:0] | |
| prio14_we | logic | |
| prio14_qs | logic [2:0] | |
| prio14_wd | logic [2:0] | |
| prio15_we | logic | |
| prio15_qs | logic [2:0] | |
| prio15_wd | logic [2:0] | |
| prio16_we | logic | |
| prio16_qs | logic [2:0] | |
| prio16_wd | logic [2:0] | |
| prio17_we | logic | |
| prio17_qs | logic [2:0] | |
| prio17_wd | logic [2:0] | |
| prio18_we | logic | |
| prio18_qs | logic [2:0] | |
| prio18_wd | logic [2:0] | |
| prio19_we | logic | |
| prio19_qs | logic [2:0] | |
| prio19_wd | logic [2:0] | |
| prio20_we | logic | |
| prio20_qs | logic [2:0] | |
| prio20_wd | logic [2:0] | |
| prio21_we | logic | |
| prio21_qs | logic [2:0] | |
| prio21_wd | logic [2:0] | |
| prio22_we | logic | |
| prio22_qs | logic [2:0] | |
| prio22_wd | logic [2:0] | |
| prio23_we | logic | |
| prio23_qs | logic [2:0] | |
| prio23_wd | logic [2:0] | |
| prio24_we | logic | |
| prio24_qs | logic [2:0] | |
| prio24_wd | logic [2:0] | |
| prio25_we | logic | |
| prio25_qs | logic [2:0] | |
| prio25_wd | logic [2:0] | |
| prio26_we | logic | |
| prio26_qs | logic [2:0] | |
| prio26_wd | logic [2:0] | |
| prio27_we | logic | |
| prio27_qs | logic [2:0] | |
| prio27_wd | logic [2:0] | |
| prio28_we | logic | |
| prio28_qs | logic [2:0] | |
| prio28_wd | logic [2:0] | |
| prio29_we | logic | |
| prio29_qs | logic [2:0] | |
| prio29_wd | logic [2:0] | |
| prio30_we | logic | |
| prio30_qs | logic [2:0] | |
| prio30_wd | logic [2:0] | |
| prio31_we | logic | |
| prio31_qs | logic [2:0] | |
| prio31_wd | logic [2:0] | |
| ie0_we | logic | |
| ie0_e_0_qs | logic | |
| ie0_e_0_wd | logic | |
| ie0_e_1_qs | logic | |
| ie0_e_1_wd | logic | |
| ie0_e_2_qs | logic | |
| ie0_e_2_wd | logic | |
| ie0_e_3_qs | logic | |
| ie0_e_3_wd | logic | |
| ie0_e_4_qs | logic | |
| ie0_e_4_wd | logic | |
| ie0_e_5_qs | logic | |
| ie0_e_5_wd | logic | |
| ie0_e_6_qs | logic | |
| ie0_e_6_wd | logic | |
| ie0_e_7_qs | logic | |
| ie0_e_7_wd | logic | |
| ie0_e_8_qs | logic | |
| ie0_e_8_wd | logic | |
| ie0_e_9_qs | logic | |
| ie0_e_9_wd | logic | |
| ie0_e_10_qs | logic | |
| ie0_e_10_wd | logic | |
| ie0_e_11_qs | logic | |
| ie0_e_11_wd | logic | |
| ie0_e_12_qs | logic | |
| ie0_e_12_wd | logic | |
| ie0_e_13_qs | logic | |
| ie0_e_13_wd | logic | |
| ie0_e_14_qs | logic | |
| ie0_e_14_wd | logic | |
| ie0_e_15_qs | logic | |
| ie0_e_15_wd | logic | |
| ie0_e_16_qs | logic | |
| ie0_e_16_wd | logic | |
| ie0_e_17_qs | logic | |
| ie0_e_17_wd | logic | |
| ie0_e_18_qs | logic | |
| ie0_e_18_wd | logic | |
| ie0_e_19_qs | logic | |
| ie0_e_19_wd | logic | |
| ie0_e_20_qs | logic | |
| ie0_e_20_wd | logic | |
| ie0_e_21_qs | logic | |
| ie0_e_21_wd | logic | |
| ie0_e_22_qs | logic | |
| ie0_e_22_wd | logic | |
| ie0_e_23_qs | logic | |
| ie0_e_23_wd | logic | |
| ie0_e_24_qs | logic | |
| ie0_e_24_wd | logic | |
| ie0_e_25_qs | logic | |
| ie0_e_25_wd | logic | |
| ie0_e_26_qs | logic | |
| ie0_e_26_wd | logic | |
| ie0_e_27_qs | logic | |
| ie0_e_27_wd | logic | |
| ie0_e_28_qs | logic | |
| ie0_e_28_wd | logic | |
| ie0_e_29_qs | logic | |
| ie0_e_29_wd | logic | |
| ie0_e_30_qs | logic | |
| ie0_e_30_wd | logic | |
| ie0_e_31_qs | logic | |
| ie0_e_31_wd | logic | |
| threshold0_we | logic | |
| threshold0_qs | logic [2:0] | |
| threshold0_wd | logic [2:0] | |
| cc0_re | logic | |
| cc0_we | logic | |
| cc0_qs | logic [4:0] | |
| cc0_wd | logic [4:0] | |
| msip0_we | logic | |
| msip0_qs | logic | |
| msip0_wd | logic | |
| alert_test_we | logic | |
| alert_test_wd | logic | |
| addr_hit | logic [38:0] | |
| shadow_busy | logic | shadow busy |
| reg_busy_sel | logic | register busy |
| unused_wdata | logic | Unused signal tieoff wdata / byte enable are not always fully used add a blanket unused statement to handle lint waivers |
| unused_be | logic |
Constants
| Name | Type | Value | Description |
|---|---|---|---|
| AW | int | 10 | |
| DW | int | 32 | |
| DBW | int | DW/8 | Byte Width |
Processes
- unnamed: ( @(posedge clk_i or negedge rst_ni) )
Type: always_ff
- unnamed: ( )
Type: always_comb
- unnamed: ( )
Type: always_comb
Description
Check sub-word write is permitted
- unnamed: ( )
Type: always_comb
Description
Read data return
- unnamed: ( )
Type: always_comb
Instantiations
- u_chk: tlul_cmd_intg_chk
- u_rsp_intg_gen: tlul_rsp_intg_gen
- u_reg_if: tlul_adapter_reg
- u_prio0: prim_subreg
Description
R[prio0]: V(False)
- u_prio1: prim_subreg
Description
R[prio1]: V(False)
- u_prio2: prim_subreg
Description
R[prio2]: V(False)
- u_prio3: prim_subreg
Description
R[prio3]: V(False)
- u_prio4: prim_subreg
Description
R[prio4]: V(False)
- u_prio5: prim_subreg
Description
R[prio5]: V(False)
- u_prio6: prim_subreg
Description
R[prio6]: V(False)
- u_prio7: prim_subreg
Description
R[prio7]: V(False)
- u_prio8: prim_subreg
Description
R[prio8]: V(False)
- u_prio9: prim_subreg
Description
R[prio9]: V(False)
- u_prio10: prim_subreg
Description
R[prio10]: V(False)
- u_prio11: prim_subreg
Description
R[prio11]: V(False)
- u_prio12: prim_subreg
Description
R[prio12]: V(False)
- u_prio13: prim_subreg
Description
R[prio13]: V(False)
- u_prio14: prim_subreg
Description
R[prio14]: V(False)
- u_prio15: prim_subreg
Description
R[prio15]: V(False)
- u_prio16: prim_subreg
Description
R[prio16]: V(False)
- u_prio17: prim_subreg
Description
R[prio17]: V(False)
- u_prio18: prim_subreg
Description
R[prio18]: V(False)
- u_prio19: prim_subreg
Description
R[prio19]: V(False)
- u_prio20: prim_subreg
Description
R[prio20]: V(False)
- u_prio21: prim_subreg
Description
R[prio21]: V(False)
- u_prio22: prim_subreg
Description
R[prio22]: V(False)
- u_prio23: prim_subreg
Description
R[prio23]: V(False)
- u_prio24: prim_subreg
Description
R[prio24]: V(False)
- u_prio25: prim_subreg
Description
R[prio25]: V(False)
- u_prio26: prim_subreg
Description
R[prio26]: V(False)
- u_prio27: prim_subreg
Description
R[prio27]: V(False)
- u_prio28: prim_subreg
Description
R[prio28]: V(False)
- u_prio29: prim_subreg
Description
R[prio29]: V(False)
- u_prio30: prim_subreg
Description
R[prio30]: V(False)
- u_prio31: prim_subreg
Description
R[prio31]: V(False)
- u_threshold0: prim_subreg
Description
R[threshold0]: V(False)
- u_cc0: prim_subreg_ext
Description
R[cc0]: V(True)
- u_msip0: prim_subreg
Description
R[msip0]: V(False)
- u_alert_test: prim_subreg_ext
Description
R[alert_test]: V(True)