Package: rv_timer_reg_pkg

Description

Copyright lowRISC contributors.
Licensed under the Apache License, Version 2.0, see LICENSE for details.
SPDX-License-Identifier: Apache-2.0

Register Package auto-generated by reggen containing data structure

Constants

Name Type Value Description
N_HARTS int 1
N_TIMERS int 1
NumAlerts int 1
BlockAw int 9 Address widths within the block
BlockAw logic [BlockAw-1:0] undefined Register offsets
BlockAw logic [BlockAw-1:0] 4
BlockAw logic [BlockAw-1:0] 100
BlockAw logic [BlockAw-1:0] 104
BlockAw logic [BlockAw-1:0] 108
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 110
BlockAw logic [BlockAw-1:0] 114
BlockAw logic [BlockAw-1:0] 118
BlockAw logic [BlockAw-1:0] c
RV_TIMER_ALERT_TEST_RESVAL logic [0:0] undefined Reset values for hwext registers and their fields
RV_TIMER_ALERT_TEST_FATAL_FAULT_RESVAL logic [0:0] undefined
RV_TIMER_INTR_TEST0_RESVAL logic [0:0]
RV_TIMER_PERMIT logic [3:0] undefined Register width information to check illegal writes

Types

Name Type Description
rv_timer_reg2hw_alert_test_reg_t struct packed {
logic q;
logic qe;
}		 ////////////////////////// Typedefs for registers // //////////////////////////
rv_timer_reg2hw_ctrl_mreg_t struct packed {
logic q;
}
rv_timer_reg2hw_cfg0_reg_t struct packed {
struct packed {
logic [11:0] q;
} prescale;
struct packed {
logic [7:0] q;
} step;
}
rv_timer_reg2hw_timer_v_lower0_reg_t struct packed {
logic [31:0] q;
}
rv_timer_reg2hw_timer_v_upper0_reg_t struct packed {
logic [31:0] q;
}
rv_timer_reg2hw_compare_lower0_0_reg_t struct packed {
logic [31:0] q;
logic qe;
}
rv_timer_reg2hw_compare_upper0_0_reg_t struct packed {
logic [31:0] q;
logic qe;
}
rv_timer_reg2hw_intr_enable0_mreg_t struct packed {
logic q;
}
rv_timer_reg2hw_intr_state0_mreg_t struct packed {
logic q;
}
rv_timer_reg2hw_intr_test0_mreg_t struct packed {
logic q;
logic qe;
}
rv_timer_hw2reg_timer_v_lower0_reg_t struct packed {
logic [31:0] d;
logic de;
}
rv_timer_hw2reg_timer_v_upper0_reg_t struct packed {
logic [31:0] d;
logic de;
}
rv_timer_hw2reg_intr_state0_mreg_t struct packed {
logic d;
logic de;
}
rv_timer_reg2hw_ctrl_mreg_t struct packed {
rv_timer_reg2hw_alert_test_reg_t alert_test;
rv_timer_reg2hw_ctrl_mreg_t [0:0] ctrl;
rv_timer_reg2hw_cfg0_reg_t cfg0;
rv_timer_reg2hw_timer_v_lower0_reg_t timer_v_lower0;
rv_timer_reg2hw_timer_v_upper0_reg_t timer_v_upper0;
rv_timer_reg2hw_compare_lower0_0_reg_t compare_lower0_0;
rv_timer_reg2hw_compare_upper0_0_reg_t compare_upper0_0;
rv_timer_reg2hw_intr_enable0_mreg_t [0:0] intr_enable0;
rv_timer_reg2hw_intr_state0_mreg_t [0:0] intr_state0;
rv_timer_reg2hw_intr_test0_mreg_t [0:0] intr_test0;
}		 Register -> HW type
rv_timer_hw2reg_intr_state0_mreg_t struct packed {
rv_timer_hw2reg_timer_v_lower0_reg_t timer_v_lower0;
rv_timer_hw2reg_timer_v_upper0_reg_t timer_v_upper0;
rv_timer_hw2reg_intr_state0_mreg_t [0:0] intr_state0;
}		 HW -> register type