Package: spi_device_reg_pkg

Description

Copyright lowRISC contributors.
Licensed under the Apache License, Version 2.0, see LICENSE for details.
SPDX-License-Identifier: Apache-2.0

Register Package auto-generated by reggen containing data structure

Constants

Name Type Value Description
SramDepth int unsigned 1024
NumCmdInfo int unsigned 24
NumAlerts int 1
BlockAw int 13 Address widths within the block
BlockAw logic [BlockAw-1:0] undefined Register offsets
BlockAw logic [BlockAw-1:0] 4
BlockAw logic [BlockAw-1:0] 8
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 10
BlockAw logic [BlockAw-1:0] 14
BlockAw logic [BlockAw-1:0] 18
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 20
BlockAw logic [BlockAw-1:0] 24
BlockAw logic [BlockAw-1:0] 28
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 30
BlockAw logic [BlockAw-1:0] 34
BlockAw logic [BlockAw-1:0] 38
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 40
BlockAw logic [BlockAw-1:0] 44
BlockAw logic [BlockAw-1:0] 48
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 50
BlockAw logic [BlockAw-1:0] 54
BlockAw logic [BlockAw-1:0] 58
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 60
BlockAw logic [BlockAw-1:0] 64
BlockAw logic [BlockAw-1:0] 68
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 70
BlockAw logic [BlockAw-1:0] 74
BlockAw logic [BlockAw-1:0] 78
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 80
BlockAw logic [BlockAw-1:0] 84
BlockAw logic [BlockAw-1:0] 88
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 90
BlockAw logic [BlockAw-1:0] 94
BlockAw logic [BlockAw-1:0] 98
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] a0
BlockAw logic [BlockAw-1:0] a4
BlockAw logic [BlockAw-1:0] a8
BlockAw logic [BlockAw-1:0] ac
BlockAw logic [BlockAw-1:0] b0
BlockAw logic [BlockAw-1:0] b4
BlockAw logic [BlockAw-1:0] b8
BlockAw logic [BlockAw-1:0] bc
BlockAw logic [BlockAw-1:0] c0
BlockAw logic [BlockAw-1:0] c4
BlockAw logic [BlockAw-1:0] c8
BlockAw logic [BlockAw-1:0] cc
BlockAw logic [BlockAw-1:0] d0
BlockAw logic [BlockAw-1:0] d4
SPI_DEVICE_INTR_TEST_RESVAL logic [5:0] undefined Reset values for hwext registers and their fields
SPI_DEVICE_INTR_TEST_RXF_RESVAL logic [0:0] undefined
SPI_DEVICE_INTR_TEST_RXLVL_RESVAL logic [0:0] undefined
SPI_DEVICE_INTR_TEST_TXLVL_RESVAL logic [0:0] undefined
SPI_DEVICE_INTR_TEST_RXERR_RESVAL logic [0:0] undefined
SPI_DEVICE_INTR_TEST_RXOVERFLOW_RESVAL logic [0:0] undefined
SPI_DEVICE_INTR_TEST_TXUNDERFLOW_RESVAL logic [0:0] undefined
SPI_DEVICE_ALERT_TEST_RESVAL logic [0:0] undefined
SPI_DEVICE_ALERT_TEST_FATAL_FAULT_RESVAL logic [0:0] undefined
SPI_DEVICE_ASYNC_FIFO_LEVEL_RESVAL logic [23:0] undefined
SPI_DEVICE_STATUS_RESVAL logic [5:0] a
SPI_DEVICE_STATUS_RXF_EMPTY_RESVAL logic [0:0] undefined
SPI_DEVICE_STATUS_TXF_EMPTY_RESVAL logic [0:0] undefined
SPI_DEVICE_STATUS_ABORT_DONE_RESVAL logic [0:0] undefined
SPI_DEVICE_STATUS_CSB_RESVAL logic [0:0] undefined
SPI_DEVICE_LAST_READ_ADDR_RESVAL logic [31:0] undefined
SPI_DEVICE_FLASH_STATUS_RESVAL logic [23:0] undefined
SPI_DEVICE_UPLOAD_CMDFIFO_RESVAL logic [7:0] undefined
SPI_DEVICE_UPLOAD_ADDRFIFO_RESVAL logic [31:0] logic [BlockAw-1:0]
SPI_DEVICE_BUFFER_SIZE int unsigned 1000
SPI_DEVICE_PERMIT logic [3:0] undefined Register width information to check illegal writes

Types

Name Type Description
spi_device_reg2hw_intr_state_reg_t struct packed {
struct packed {
logic q;
} rxf;
struct packed {
logic q;
} rxlvl;
struct packed {
logic q;
} txlvl;
struct packed {
logic q;
} rxerr;
struct packed {
logic q;
} rxoverflow;
struct packed {
logic q;
} txunderflow;
}		 ////////////////////////// Typedefs for registers // //////////////////////////
spi_device_reg2hw_intr_enable_reg_t struct packed {
struct packed {
logic q;
} rxf;
struct packed {
logic q;
} rxlvl;
struct packed {
logic q;
} txlvl;
struct packed {
logic q;
} rxerr;
struct packed {
logic q;
} rxoverflow;
struct packed {
logic q;
} txunderflow;
}
spi_device_reg2hw_intr_test_reg_t struct packed {
struct packed {
logic q;
logic qe;
} rxf;
struct packed {
logic q;
logic qe;
} rxlvl;
struct packed {
logic q;
logic qe;
} txlvl;
struct packed {
logic q;
logic qe;
} rxerr;
struct packed {
logic q;
logic qe;
} rxoverflow;
struct packed {
logic q;
logic qe;
} txunderflow;
}
spi_device_reg2hw_alert_test_reg_t struct packed {
logic q;
logic qe;
}
spi_device_reg2hw_control_reg_t struct packed {
struct packed {
logic q;
} abort;
struct packed {
logic [1:0] q;
} mode;
struct packed {
logic q;
} rst_txfifo;
struct packed {
logic q;
} rst_rxfifo;
struct packed {
logic q;
} sram_clk_en;
}
spi_device_reg2hw_cfg_reg_t struct packed {
struct packed {
logic q;
} cpol;
struct packed {
logic q;
} cpha;
struct packed {
logic q;
} tx_order;
struct packed {
logic q;
} rx_order;
struct packed {
logic [7:0] q;
} timer_v;
struct packed {
logic q;
} addr_4b_en;
}
spi_device_reg2hw_fifo_level_reg_t struct packed {
struct packed {
logic [15:0] q;
} rxlvl;
struct packed {
logic [15:0] q;
} txlvl;
}
spi_device_reg2hw_rxf_ptr_reg_t struct packed {
struct packed {
logic [15:0] q;
} rptr;
}
spi_device_reg2hw_txf_ptr_reg_t struct packed {
struct packed {
logic [15:0] q;
} wptr;
}
spi_device_reg2hw_rxf_addr_reg_t struct packed {
struct packed {
logic [15:0] q;
} base;
struct packed {
logic [15:0] q;
} limit;
}
spi_device_reg2hw_txf_addr_reg_t struct packed {
struct packed {
logic [15:0] q;
} base;
struct packed {
logic [15:0] q;
} limit;
}
spi_device_reg2hw_flash_status_reg_t struct packed {
struct packed {
logic q;
logic qe;
} busy;
struct packed {
logic [22:0] q;
logic qe;
} status;
}
spi_device_reg2hw_jedec_id_reg_t struct packed {
struct packed {
logic [15:0] q;
} id;
struct packed {
logic [7:0] q;
} mf;
}
spi_device_reg2hw_read_threshold_reg_t struct packed {
logic [9:0] q;
}
spi_device_reg2hw_upload_cmdfifo_reg_t struct packed {
logic [7:0] q;
logic re;
}
spi_device_reg2hw_upload_addrfifo_reg_t struct packed {
logic [31:0] q;
logic re;
}
spi_device_reg2hw_cmd_filter_mreg_t struct packed {
logic q;
}
spi_device_reg2hw_addr_swap_mask_reg_t struct packed {
logic [31:0] q;
}
spi_device_reg2hw_addr_swap_data_reg_t struct packed {
logic [31:0] q;
}
spi_device_reg2hw_cmd_info_mreg_t struct packed {
struct packed {
logic [7:0] q;
} opcode;
struct packed {
logic q;
} addr_en;
struct packed {
logic q;
} addr_swap_en;
struct packed {
logic q;
} addr_4b_affected;
struct packed {
logic q;
} mbyte_en;
struct packed {
logic [2:0] q;
} dummy_size;
struct packed {
logic q;
} dummy_en;
struct packed {
logic [3:0] q;
} payload_en;
struct packed {
logic q;
} payload_dir;
struct packed {
logic q;
} upload;
struct packed {
logic q;
} busy;
}
spi_device_hw2reg_intr_state_reg_t struct packed {
struct packed {
logic d;
logic de;
} rxf;
struct packed {
logic d;
logic de;
} rxlvl;
struct packed {
logic d;
logic de;
} txlvl;
struct packed {
logic d;
logic de;
} rxerr;
struct packed {
logic d;
logic de;
} rxoverflow;
struct packed {
logic d;
logic de;
} txunderflow;
}
spi_device_hw2reg_async_fifo_level_reg_t struct packed {
struct packed {
logic [7:0] d;
} rxlvl;
struct packed {
logic [7:0] d;
} txlvl;
}
spi_device_hw2reg_status_reg_t struct packed {
struct packed {
logic d;
} rxf_full;
struct packed {
logic d;
} rxf_empty;
struct packed {
logic d;
} txf_full;
struct packed {
logic d;
} txf_empty;
struct packed {
logic d;
} abort_done;
struct packed {
logic d;
} csb;
}
spi_device_hw2reg_rxf_ptr_reg_t struct packed {
struct packed {
logic [15:0] d;
logic de;
} wptr;
}
spi_device_hw2reg_txf_ptr_reg_t struct packed {
struct packed {
logic [15:0] d;
logic de;
} rptr;
}
spi_device_hw2reg_last_read_addr_reg_t struct packed {
logic [31:0] d;
}
spi_device_hw2reg_flash_status_reg_t struct packed {
struct packed {
logic d;
} busy;
struct packed {
logic [22:0] d;
} status;
}
spi_device_hw2reg_upload_status_reg_t struct packed {
struct packed {
logic [4:0] d;
logic de;
} cmdfifo_depth;
struct packed {
logic d;
logic de;
} cmdfifo_notempty;
struct packed {
logic [4:0] d;
logic de;
} addrfifo_depth;
struct packed {
logic d;
logic de;
} addrfifo_notempty;
struct packed {
logic [8:0] d;
logic de;
} payload_depth;
}
spi_device_hw2reg_upload_cmdfifo_reg_t struct packed {
logic [7:0] d;
}
spi_device_hw2reg_upload_addrfifo_reg_t struct packed {
logic [31:0] d;
}
spi_device_reg2hw_cmd_filter_mreg_t struct packed {
spi_device_reg2hw_intr_state_reg_t intr_state;
spi_device_reg2hw_intr_enable_reg_t intr_enable;
spi_device_reg2hw_intr_test_reg_t intr_test;
spi_device_reg2hw_alert_test_reg_t alert_test;
spi_device_reg2hw_control_reg_t control;
spi_device_reg2hw_cfg_reg_t cfg;
spi_device_reg2hw_fifo_level_reg_t fifo_level;
spi_device_reg2hw_rxf_ptr_reg_t rxf_ptr;
spi_device_reg2hw_txf_ptr_reg_t txf_ptr;
spi_device_reg2hw_rxf_addr_reg_t rxf_addr;
spi_device_reg2hw_txf_addr_reg_t txf_addr;
spi_device_reg2hw_flash_status_reg_t flash_status;
spi_device_reg2hw_jedec_id_reg_t jedec_id;
spi_device_reg2hw_read_threshold_reg_t read_threshold;
spi_device_reg2hw_upload_cmdfifo_reg_t upload_cmdfifo;
spi_device_reg2hw_upload_addrfifo_reg_t upload_addrfifo;
spi_device_reg2hw_cmd_filter_mreg_t [255:0] cmd_filter;
spi_device_reg2hw_addr_swap_mask_reg_t addr_swap_mask;
spi_device_reg2hw_addr_swap_data_reg_t addr_swap_data;
spi_device_reg2hw_cmd_info_mreg_t [23:0] cmd_info;
}		 Register -> HW type
spi_device_hw2reg_t struct packed {
spi_device_hw2reg_intr_state_reg_t intr_state;
spi_device_hw2reg_async_fifo_level_reg_t async_fifo_level;
spi_device_hw2reg_status_reg_t status;
spi_device_hw2reg_rxf_ptr_reg_t rxf_ptr;
spi_device_hw2reg_txf_ptr_reg_t txf_ptr;
spi_device_hw2reg_last_read_addr_reg_t last_read_addr;
spi_device_hw2reg_flash_status_reg_t flash_status;
spi_device_hw2reg_upload_status_reg_t upload_status;
spi_device_hw2reg_upload_cmdfifo_reg_t upload_cmdfifo;
spi_device_hw2reg_upload_addrfifo_reg_t upload_addrfifo;
}		 HW -> register type
spi_device_id_e enum int {
SPI_DEVICE_INTR_STATE,
SPI_DEVICE_INTR_ENABLE,
SPI_DEVICE_INTR_TEST,
SPI_DEVICE_ALERT_TEST,
SPI_DEVICE_CONTROL,
SPI_DEVICE_CFG,
SPI_DEVICE_FIFO_LEVEL,
SPI_DEVICE_ASYNC_FIFO_LEVEL,
SPI_DEVICE_STATUS,
SPI_DEVICE_RXF_PTR,
SPI_DEVICE_TXF_PTR,
SPI_DEVICE_RXF_ADDR,
SPI_DEVICE_TXF_ADDR,
SPI_DEVICE_LAST_READ_ADDR,
SPI_DEVICE_FLASH_STATUS,
SPI_DEVICE_JEDEC_ID,
SPI_DEVICE_READ_THRESHOLD,
SPI_DEVICE_UPLOAD_STATUS,
SPI_DEVICE_UPLOAD_CMDFIFO,
SPI_DEVICE_UPLOAD_ADDRFIFO,
SPI_DEVICE_CMD_FILTER_0,
SPI_DEVICE_CMD_FILTER_1,
SPI_DEVICE_CMD_FILTER_2,
SPI_DEVICE_CMD_FILTER_3,
SPI_DEVICE_CMD_FILTER_4,
SPI_DEVICE_CMD_FILTER_5,
SPI_DEVICE_CMD_FILTER_6,
SPI_DEVICE_CMD_FILTER_7,
SPI_DEVICE_ADDR_SWAP_MASK,
SPI_DEVICE_ADDR_SWAP_DATA,
SPI_DEVICE_CMD_INFO_0,
SPI_DEVICE_CMD_INFO_1,
SPI_DEVICE_CMD_INFO_2,
SPI_DEVICE_CMD_INFO_3,
SPI_DEVICE_CMD_INFO_4,
SPI_DEVICE_CMD_INFO_5,
SPI_DEVICE_CMD_INFO_6,
SPI_DEVICE_CMD_INFO_7,
SPI_DEVICE_CMD_INFO_8,
SPI_DEVICE_CMD_INFO_9,
SPI_DEVICE_CMD_INFO_10,
SPI_DEVICE_CMD_INFO_11,
SPI_DEVICE_CMD_INFO_12,
SPI_DEVICE_CMD_INFO_13,
SPI_DEVICE_CMD_INFO_14,
SPI_DEVICE_CMD_INFO_15,
SPI_DEVICE_CMD_INFO_16,
SPI_DEVICE_CMD_INFO_17,
SPI_DEVICE_CMD_INFO_18,
SPI_DEVICE_CMD_INFO_19,
SPI_DEVICE_CMD_INFO_20,
SPI_DEVICE_CMD_INFO_21,
SPI_DEVICE_CMD_INFO_22,
SPI_DEVICE_CMD_INFO_23 }		 Register index