Entity: spi_host_reg_top

File: spi_host_reg_top.sv

Diagram

Description

Copyright lowRISC contributors. Licensed under the Apache License, Version 2.0, see LICENSE for details. SPDX-License-Identifier: Apache-2.0

Ports

Port name	Direction	Description
clk_i	input
rst_ni	input
tl_i	input
tl_o	output
tl_win_o	output	Output port for window
tl_win_i	input
reg2hw	output	Write
hw2reg	input	Read
intg_err_o	output	Integrity check errors
devmode_i	input	If 1, explicit error return for unmapped register access

Signals

Name	Type	Description
reg_we	logic	register signals
reg_re	logic
reg_addr	logic [AW-1:0]
reg_wdata	logic [DW-1:0]
reg_be	logic [DBW-1:0]
reg_rdata	logic [DW-1:0]
reg_error	logic
addrmiss	logic
wr_err	logic
reg_rdata_next	logic [DW-1:0]
reg_busy	logic
tl_reg_h2d	tlul_pkg::tl_h2d_t
tl_reg_d2h	tlul_pkg::tl_d2h_t
intg_err	logic	incoming payload check
intg_err_q	logic
tl_o_pre	tlul_pkg::tl_d2h_t	outgoing integrity generation
tl_socket_h2d	tlul_pkg::tl_h2d_t
tl_socket_d2h	tlul_pkg::tl_d2h_t
reg_steer	logic [1:0]
intr_state_we	logic	Define SW related signals Format: {wd
intr_state_error_qs	logic
intr_state_error_wd	logic
intr_state_spi_event_qs	logic
intr_state_spi_event_wd	logic
intr_enable_we	logic
intr_enable_error_qs	logic
intr_enable_error_wd	logic
intr_enable_spi_event_qs	logic
intr_enable_spi_event_wd	logic
intr_test_we	logic
intr_test_error_wd	logic
intr_test_spi_event_wd	logic
alert_test_we	logic
alert_test_wd	logic
control_we	logic
control_rx_watermark_qs	logic [7:0]
control_rx_watermark_wd	logic [7:0]
control_tx_watermark_qs	logic [7:0]
control_tx_watermark_wd	logic [7:0]
control_sw_rst_qs	logic
control_sw_rst_wd	logic
control_spien_qs	logic
control_spien_wd	logic
status_txqd_qs	logic [7:0]
status_rxqd_qs	logic [7:0]
status_rxwm_qs	logic
status_byteorder_qs	logic
status_rxstall_qs	logic
status_rxempty_qs	logic
status_rxfull_qs	logic
status_txwm_qs	logic
status_txstall_qs	logic
status_txempty_qs	logic
status_txfull_qs	logic
status_active_qs	logic
status_ready_qs	logic
configopts_we	logic
configopts_clkdiv_0_qs	logic [15:0]
configopts_clkdiv_0_wd	logic [15:0]
configopts_csnidle_0_qs	logic [3:0]
configopts_csnidle_0_wd	logic [3:0]
configopts_csntrail_0_qs	logic [3:0]
configopts_csntrail_0_wd	logic [3:0]
configopts_csnlead_0_qs	logic [3:0]
configopts_csnlead_0_wd	logic [3:0]
configopts_fullcyc_0_qs	logic
configopts_fullcyc_0_wd	logic
configopts_cpha_0_qs	logic
configopts_cpha_0_wd	logic
configopts_cpol_0_qs	logic
configopts_cpol_0_wd	logic
csid_we	logic
csid_qs	logic [31:0]
csid_wd	logic [31:0]
command_we	logic
command_len_qs	logic [8:0]
command_len_wd	logic [8:0]
command_csaat_qs	logic
command_csaat_wd	logic
command_speed_qs	logic [1:0]
command_speed_wd	logic [1:0]
command_direction_qs	logic [1:0]
command_direction_wd	logic [1:0]
error_enable_we	logic
error_enable_cmdbusy_qs	logic
error_enable_cmdbusy_wd	logic
error_enable_overflow_qs	logic
error_enable_overflow_wd	logic
error_enable_underflow_qs	logic
error_enable_underflow_wd	logic
error_enable_cmdinval_qs	logic
error_enable_cmdinval_wd	logic
error_enable_csidinval_qs	logic
error_enable_csidinval_wd	logic
error_status_we	logic
error_status_cmdbusy_qs	logic
error_status_cmdbusy_wd	logic
error_status_overflow_qs	logic
error_status_overflow_wd	logic
error_status_underflow_qs	logic
error_status_underflow_wd	logic
error_status_cmdinval_qs	logic
error_status_cmdinval_wd	logic
error_status_csidinval_qs	logic
error_status_csidinval_wd	logic
event_enable_we	logic
event_enable_rxfull_qs	logic
event_enable_rxfull_wd	logic
event_enable_txempty_qs	logic
event_enable_txempty_wd	logic
event_enable_rxwm_qs	logic
event_enable_rxwm_wd	logic
event_enable_txwm_qs	logic
event_enable_txwm_wd	logic
event_enable_ready_qs	logic
event_enable_ready_wd	logic
event_enable_idle_qs	logic
event_enable_idle_wd	logic
addr_hit	logic [11:0]
shadow_busy	logic	shadow busy
reg_busy_sel	logic	register busy
unused_wdata	logic	Unused signal tieoff wdata / byte enable are not always fully used add a blanket unused statement to handle lint waivers
unused_be	logic

Constants

Name	Type	Value	Description
AW	int	6
DW	int	32
DBW	int	DW/8	Byte Width

Processes

unnamed: ( @(posedge clk_i or negedge rst_ni) )

Type: always_ff

unnamed: ( )

Type: always_comb

Description
Create steering logic

unnamed: ( )

Type: always_comb

unnamed: ( )

Type: always_comb

Description
Check sub-word write is permitted

unnamed: ( )

Type: always_comb

Description
Read data return

unnamed: ( )

Type: always_comb

Instantiations

u_chk: tlul_cmd_intg_chk

u_rsp_intg_gen: tlul_rsp_intg_gen

u_socket: tlul_socket_1n

Description
Create Socket_1n

u_reg_if: tlul_adapter_reg

u_intr_state_error: prim_subreg

Description
Register instances
R[intr_state]: V(False)
F[error]: 0:0

u_intr_state_spi_event: prim_subreg

Description
F[spi_event]: 1:1

u_intr_enable_error: prim_subreg

Description
R[intr_enable]: V(False)
F[error]: 0:0

u_intr_enable_spi_event: prim_subreg

Description
F[spi_event]: 1:1

u_intr_test_error: prim_subreg_ext

Description
R[intr_test]: V(True)
F[error]: 0:0

u_intr_test_spi_event: prim_subreg_ext

Description
F[spi_event]: 1:1

u_alert_test: prim_subreg_ext

Description
R[alert_test]: V(True)

u_control_rx_watermark: prim_subreg

Description
R[control]: V(False)
F[rx_watermark]: 7:0

u_control_tx_watermark: prim_subreg

Description
F[tx_watermark]: 15:8

u_control_sw_rst: prim_subreg

Description
F[sw_rst]: 30:30

u_control_spien: prim_subreg

Description
F[spien]: 31:31

u_status_txqd: prim_subreg

Description
R[status]: V(False)
F[txqd]: 7:0

u_status_rxqd: prim_subreg

Description
F[rxqd]: 15:8

u_status_rxwm: prim_subreg

Description
F[rxwm]: 20:20

u_status_byteorder: prim_subreg

Description
F[byteorder]: 22:22

u_status_rxstall: prim_subreg

Description
F[rxstall]: 23:23

u_status_rxempty: prim_subreg

Description
F[rxempty]: 24:24

u_status_rxfull: prim_subreg

Description
F[rxfull]: 25:25

u_status_txwm: prim_subreg

Description
F[txwm]: 26:26

u_status_txstall: prim_subreg

Description
F[txstall]: 27:27

u_status_txempty: prim_subreg

Description
F[txempty]: 28:28

u_status_txfull: prim_subreg

Description
F[txfull]: 29:29

u_status_active: prim_subreg

Description
F[active]: 30:30

u_status_ready: prim_subreg

Description
F[ready]: 31:31

u_csid: prim_subreg

Description
R[csid]: V(False)

u_command_len: prim_subreg

Description
R[command]: V(False)
F[len]: 8:0

u_command_csaat: prim_subreg

Description
F[csaat]: 9:9

u_command_speed: prim_subreg

Description
F[speed]: 11:10

u_command_direction: prim_subreg

Description
F[direction]: 13:12

u_error_enable_cmdbusy: prim_subreg

Description
R[error_enable]: V(False)
F[cmdbusy]: 0:0

u_error_enable_overflow: prim_subreg

Description
F[overflow]: 1:1

u_error_enable_underflow: prim_subreg

Description
F[underflow]: 2:2

u_error_enable_cmdinval: prim_subreg

Description
F[cmdinval]: 3:3

u_error_enable_csidinval: prim_subreg

Description
F[csidinval]: 4:4

u_error_status_cmdbusy: prim_subreg

Description
R[error_status]: V(False)
F[cmdbusy]: 0:0

u_error_status_overflow: prim_subreg

Description
F[overflow]: 1:1

u_error_status_underflow: prim_subreg

Description
F[underflow]: 2:2

u_error_status_cmdinval: prim_subreg

Description
F[cmdinval]: 3:3

u_error_status_csidinval: prim_subreg

Description
F[csidinval]: 4:4

u_event_enable_rxfull: prim_subreg

Description
R[event_enable]: V(False)
F[rxfull]: 0:0

u_event_enable_txempty: prim_subreg

Description
F[txempty]: 1:1

u_event_enable_rxwm: prim_subreg

Description
F[rxwm]: 2:2

u_event_enable_txwm: prim_subreg

Description
F[txwm]: 3:3

u_event_enable_ready: prim_subreg

Description
F[ready]: 4:4

u_event_enable_idle: prim_subreg

Description
F[idle]: 5:5