Entity: sram_ctrl

• File: sram_ctrl.sv

Diagram

Description

Generics

Generic name	Type	Value	Description
MemSizeRam	int	32'h1000	Number of words stored in the SRAM.
NumAlerts	logic [NumAlerts-1:0]	undefined	Enable asynchronous transitions on alerts.
InstrExec	bit	1	Enables the execute from SRAM feature.
RndCnstSramKey	otp_ctrl_pkg::sram_key_t	RndCnstSramKeyDefault	Random netlist constants
RndCnstSramNonce	otp_ctrl_pkg::sram_nonce_t	RndCnstSramNonceDefault
RndCnstLfsrSeed	lfsr_seed_t	RndCnstLfsrSeedDefault
RndCnstLfsrPerm	lfsr_perm_t	RndCnstLfsrPermDefault
Depth	int unsigned	MemSizeRam >> 2	This is later on pruned to the correct width at the SRAM wrapper interface.
AddrWidth	int unsigned	prim_util_pkg::vbits(Depth)

Ports

Port name	Direction	Type	Description
clk_i	input		SRAM Clock
rst_ni	input
clk_otp_i	input		OTP Clock (for key interface)
rst_otp_ni	input
ram_tl_i	input		Bus Interface (device) for SRAM
ram_tl_o	output
regs_tl_i	input		Bus Interface (device) for CSRs
regs_tl_o	output
alert_rx_i	input	[NumAlerts-1:0]	Alert outputs.
alert_tx_o	output	[NumAlerts-1:0]
lc_escalate_en_i	input		Life-cycle escalation input (scraps the scrambling keys)
lc_hw_debug_en_i	input
otp_en_sram_ifetch_i	input		Otp configuration for sram execution
sram_otp_key_o	output		Key request to OTP (running on clk_fixed)
sram_otp_key_i	input
cfg_i	input		config

Signals

Name	Type	Description
reg2hw	sram_ctrl_regs_reg2hw_t	//////////////////////// CSR Node and Mapping // ////////////////////////
hw2reg	sram_ctrl_regs_hw2reg_t
key_d	logic [otp_ctrl_pkg::SramKeyWidth-1:0]	Key and attribute outputs to scrambling device
key_q	logic [otp_ctrl_pkg::SramKeyWidth-1:0]	Key and attribute outputs to scrambling device
nonce_d	logic [otp_ctrl_pkg::SramNonceWidth-1:0]
nonce_q	logic [otp_ctrl_pkg::SramNonceWidth-1:0]
alert_test	logic	//////////////// Alert Sender // ////////////////
bus_integ_error	logic
init_error	logic
escalate_en	lc_ctrl_pkg::lc_tx_t	/////////////////////// Escalation Triggers // ///////////////////////
escalate	logic
local_esc	logic	Aggregate external and internal escalation sources. This is used on countermeasures further below (key reset, transaction blocking and scrambling nonce reversal).
init_trig	logic	///////////////////// HW Initialization // ///////////////////// A write to the init register reloads the LFSR seed, resets the init counter and sets init_q to flag a pending initialization request.
init_req	logic [1:0]	We employ two redundant counters to guard against FI attacks. If any of the two is glitched and the two counter states do not agree, we trigger an alert.
init_done	logic [1:0]	We employ two redundant counters to guard against FI attacks. If any of the two is glitched and the two counter states do not agree, we trigger an alert.
init_q	logic [1:0]	We employ two redundant counters to guard against FI attacks. If any of the two is glitched and the two counter states do not agree, we trigger an alert.
init_cnt_q	logic [1:0][AddrWidth-1:0]
key_req	logic	////////////////////////// Scrambling Key Request // ////////////////////////// The scrambling key and nonce have to be requested from the OTP controller via a req/ack protocol. Since the OTP controller works in a different clock domain, we have to synchronize the req/ack protocol as described in more details here: https://docs.opentitan.org/hw/ip/otp_ctrl/doc/index.html#interfaces-to-sram-and-otbn-scramblers
key_ack	logic	////////////////////////// Scrambling Key Request // ////////////////////////// The scrambling key and nonce have to be requested from the OTP controller via a req/ack protocol. Since the OTP controller works in a different clock domain, we have to synchronize the req/ack protocol as described in more details here: https://docs.opentitan.org/hw/ip/otp_ctrl/doc/index.html#interfaces-to-sram-and-otbn-scramblers
key_req_pending_d	logic
key_req_pending_q	logic
key_valid	logic	The SRAM scrambling wrapper will not accept any transactions while the key req is pending or if we have escalated. Note that we're not using key_valid_q here, such that the SRAM can be used right after reset, where the keys are reset to the default netlist constant.
key_seed_valid	logic	Clear this bit on local escalation.
clk_i	prim_sync_reqack_data
rst_ni	prim_sync_reqack_data
clk_otp_i	prim_sync_reqack_data
rst_otp_ni	prim_sync_reqack_data
req_chk_i	prim_sync_reqack_data
key_req_pending_q	prim_sync_reqack_data
key_ack	prim_sync_reqack_data
req	prim_sync_reqack_data
ack	prim_sync_reqack_data
key	prim_sync_reqack_data
sram_otp_key_i	prim_sync_reqack_data
sram_otp_key_i	prim_sync_reqack_data
key_d	prim_sync_reqack_data
nonce_d	prim_sync_reqack_data
key_seed_valid	prim_sync_reqack_data
unused_csr_sigs	logic
en_ifetch	tlul_pkg::tl_instr_en_e	////////////////// SRAM Execution // //////////////////
lfsr_out	logic [LfsrWidth-1:0]	/////////////////////// Initialization LFSR // ///////////////////////
lfsr_out_integ	logic [DataWidth - 1 :0]	Compute the correct integrity alongside for the pseudo-random initialization values.
tlul_req	logic	/////////////////////////////// SRAM with scrambling device // ///////////////////////////////
tlul_gnt	logic	/////////////////////////////// SRAM with scrambling device // ///////////////////////////////
tlul_we	logic	/////////////////////////////// SRAM with scrambling device // ///////////////////////////////
tlul_addr	logic [AddrWidth-1:0]
tlul_wdata	logic [DataWidth-1:0]
tlul_wmask	logic [DataWidth-1:0]
sram_intg_error	logic
sram_req	logic
sram_gnt	logic
sram_we	logic
sram_rvalid	logic
sram_addr	logic [AddrWidth-1:0]
sram_wdata	logic [DataWidth-1:0]
sram_wmask	logic [DataWidth-1:0]
sram_rdata	logic [DataWidth-1:0]

Processes

• p_regs: ( @(posedge clk_i or negedge rst_ni) )

Instantiations

• u_reg_regs: sram_ctrl_regs_reg_top

• u_prim_alert_sender_parity: prim_alert_sender

• u_prim_lc_sync: prim_lc_sync

• u_lfsr: prim_lfsr

• u_tlul_data_integ_enc: tlul_data_integ_enc

• u_tlul_adapter_sram: tlul_adapter_sram