Entity: sram_ctrl_reg_top
- File: sram_ctrl_reg_top.sv
Diagram
Description
Copyright lowRISC contributors. Licensed under the Apache License, Version 2.0, see LICENSE for details. SPDX-License-Identifier: Apache-2.0
Register Top module auto-generated by reggen
Ports
| Port name | Direction | Type | Description |
|---|---|---|---|
| clk_i | input | ||
| rst_ni | input | ||
| tl_i | input | ||
| tl_o | output | ||
| reg2hw | output | Write | |
| hw2reg | input | Read | |
| intg_err_o | output | Integrity check errors | |
| devmode_i | input | If 1, explicit error return for unmapped register access |
Signals
| Name | Type | Description |
|---|---|---|
| reg_we | logic | register signals |
| reg_re | logic | |
| reg_addr | logic [AW-1:0] | |
| reg_wdata | logic [DW-1:0] | |
| reg_be | logic [DBW-1:0] | |
| reg_rdata | logic [DW-1:0] | |
| reg_error | logic | |
| addrmiss | logic | |
| wr_err | logic | |
| reg_rdata_next | logic [DW-1:0] | |
| reg_busy | logic | |
| tl_reg_h2d | tlul_pkg::tl_h2d_t | |
| tl_reg_d2h | tlul_pkg::tl_d2h_t | |
| intg_err | logic | incoming payload check |
| intg_err_q | logic | |
| tl_o_pre | tlul_pkg::tl_d2h_t | outgoing integrity generation |
| alert_test_we | logic | Define SW related signals Format: |
| alert_test_fatal_intg_error_wd | logic | |
| alert_test_fatal_parity_error_wd | logic | |
| status_re | logic | |
| status_error_qs | logic | |
| status_escalated_qs | logic | |
| status_scr_key_valid_qs | logic | |
| status_scr_key_seed_valid_qs | logic | |
| exec_regwen_we | logic | |
| exec_regwen_qs | logic | |
| exec_regwen_wd | logic | |
| exec_we | logic | |
| exec_qs | logic [2:0] | |
| exec_wd | logic [2:0] | |
| ctrl_regwen_we | logic | |
| ctrl_regwen_qs | logic | |
| ctrl_regwen_wd | logic | |
| ctrl_re | logic | |
| ctrl_we | logic | |
| ctrl_renew_scr_key_qs | logic | |
| ctrl_renew_scr_key_wd | logic | |
| ctrl_init_qs | logic | |
| ctrl_init_wd | logic | |
| error_address_qs | logic [31:0] | |
| addr_hit | logic [6:0] | |
| unused_wdata | logic | Unused signal tieoff wdata / byte enable are not always fully used add a blanket unused statement to handle lint waivers |
| unused_be | logic |
Constants
| Name | Type | Value | Description |
|---|---|---|---|
| AW | int | 5 | |
| DW | int | 32 | |
| DBW | int | DW/8 | Byte Width |
Processes
- unnamed: ( @(posedge clk_i or negedge rst_ni) )
Type: always_ff
- unnamed: ( )
Type: always_comb
- unnamed: ( )
Type: always_comb
Description
Check sub-word write is permitted
- unnamed: ( )
Type: always_comb
Description
Read data return
- unnamed: ( )
Type: always_comb
Description
register busy
Instantiations
- u_chk: tlul_cmd_intg_chk
- u_rsp_intg_gen: tlul_rsp_intg_gen
- u_reg_if: tlul_adapter_reg
- u_alert_test_fatal_intg_error: prim_subreg_ext
Description
Register instances
R[alert_test]: V(True)
F[fatal_intg_error]: 0:0
- u_alert_test_fatal_parity_error: prim_subreg_ext
Description
F[fatal_parity_error]: 1:1
- u_status_error: prim_subreg_ext
Description
R[status]: V(True)
F[error]: 0:0
- u_status_escalated: prim_subreg_ext
Description
F[escalated]: 1:1
- u_status_scr_key_valid: prim_subreg_ext
Description
F[scr_key_valid]: 2:2
- u_status_scr_key_seed_valid: prim_subreg_ext
Description
F[scr_key_seed_valid]: 3:3
- u_exec_regwen: prim_subreg
Description
R[exec_regwen]: V(False)
- u_exec: prim_subreg
Description
R[exec]: V(False)
- u_ctrl_regwen: prim_subreg
Description
R[ctrl_regwen]: V(False)
- u_ctrl_renew_scr_key: prim_subreg_ext
Description
R[ctrl]: V(True)
F[renew_scr_key]: 0:0
- u_ctrl_init: prim_subreg_ext
Description
F[init]: 1:1
- u_error_address: prim_subreg
Description
R[error_address]: V(False)