Package: trial1_reg_pkg

Description

Copyright lowRISC contributors.
Licensed under the Apache License, Version 2.0, see LICENSE for details.
SPDX-License-Identifier: Apache-2.0

Register Package auto-generated by reggen containing data structure

Constants

Name Type Value Description
BlockAw int 10
BlockAw logic [BlockAw-1:0] undefined Register offsets
BlockAw logic [BlockAw-1:0] 4
BlockAw logic [BlockAw-1:0] 8
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 200
BlockAw logic [BlockAw-1:0] 204
BlockAw logic [BlockAw-1:0] 208
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 210
BlockAw logic [BlockAw-1:0] 214
BlockAw logic [BlockAw-1:0] 218
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 220
BlockAw logic [BlockAw-1:0] 224
BlockAw logic [BlockAw-1:0] 228
BlockAw logic [BlockAw-1:0] c
BlockAw logic [BlockAw-1:0] 230
BlockAw logic [BlockAw-1:0] 234
BlockAw logic [BlockAw-1:0] 238
BlockAw logic [BlockAw-1:0] c
TRIAL1_RWTYPE6_RESVAL logic [31:0] c8c8c8c8 Reset values for hwext registers and their fields
TRIAL1_RWTYPE6_RWTYPE6_RESVAL logic [31:0] c8c8c8c8
TRIAL1_ROTYPE1_RESVAL logic [31:0] aa66aa
TRIAL1_ROTYPE1_ROTYPE1_RESVAL logic [31:0] aa66aa
TRIAL1_PERMIT logic [3:0] undefined Register width information to check illegal writes

Types

Name Type Description
trial1_reg2hw_rwtype0_reg_t struct packed {
logic [31:0] q;
}		 ////////////////////////// Typedefs for registers // //////////////////////////
trial1_reg2hw_rwtype1_reg_t struct packed {
struct packed {
logic q;
} field0;
struct packed {
logic q;
} field1;
struct packed {
logic q;
} field4;
struct packed {
logic [7:0] q;
} field15_8;
}
trial1_reg2hw_rwtype2_reg_t struct packed {
logic [31:0] q;
}
trial1_reg2hw_rwtype3_reg_t struct packed {
struct packed {
logic [15:0] q;
} field0;
struct packed {
logic [15:0] q;
} field1;
}
trial1_reg2hw_rwtype4_reg_t struct packed {
struct packed {
logic [15:0] q;
} field0;
struct packed {
logic [15:0] q;
} field1;
}
trial1_reg2hw_rotype0_reg_t struct packed {
logic [31:0] q;
}
trial1_reg2hw_w1ctype0_reg_t struct packed {
logic [31:0] q;
}
trial1_reg2hw_w1ctype1_reg_t struct packed {
struct packed {
logic [15:0] q;
} field0;
struct packed {
logic [15:0] q;
} field1;
}
trial1_reg2hw_w1ctype2_reg_t struct packed {
logic [31:0] q;
}
trial1_reg2hw_w1stype2_reg_t struct packed {
logic [31:0] q;
}
trial1_reg2hw_w0ctype2_reg_t struct packed {
logic [31:0] q;
}
trial1_reg2hw_r0w1ctype2_reg_t struct packed {
logic [31:0] q;
}
trial1_reg2hw_rctype0_reg_t struct packed {
logic [31:0] q;
}
trial1_reg2hw_wotype0_reg_t struct packed {
logic [31:0] q;
}
trial1_reg2hw_mixtype0_reg_t struct packed {
struct packed {
logic [3:0] q;
} field0;
struct packed {
logic [3:0] q;
} field1;
struct packed {
logic [3:0] q;
} field2;
struct packed {
logic [3:0] q;
} field3;
struct packed {
logic [3:0] q;
} field4;
struct packed {
logic [3:0] q;
} field5;
struct packed {
logic [3:0] q;
} field6;
struct packed {
logic [3:0] q;
} field7;
}
trial1_reg2hw_rwtype5_reg_t struct packed {
logic [31:0] q;
logic qe;
}
trial1_reg2hw_rwtype6_reg_t struct packed {
logic [31:0] q;
logic qe;
}
trial1_reg2hw_rotype1_reg_t struct packed {
logic [31:0] q;
}
trial1_hw2reg_rwtype2_reg_t struct packed {
logic [31:0] d;
logic de;
}
trial1_hw2reg_rwtype3_reg_t struct packed {
struct packed {
logic [15:0] d;
logic de;
} field0;
struct packed {
logic [15:0] d;
logic de;
} field1;
}
trial1_hw2reg_rotype0_reg_t struct packed {
logic [31:0] d;
logic de;
}
trial1_hw2reg_w1ctype2_reg_t struct packed {
logic [31:0] d;
logic de;
}
trial1_hw2reg_w1stype2_reg_t struct packed {
logic [31:0] d;
logic de;
}
trial1_hw2reg_w0ctype2_reg_t struct packed {
logic [31:0] d;
logic de;
}
trial1_hw2reg_r0w1ctype2_reg_t struct packed {
logic [31:0] d;
logic de;
}
trial1_hw2reg_rctype0_reg_t struct packed {
logic [31:0] d;
logic de;
}
trial1_hw2reg_mixtype0_reg_t struct packed {
struct packed {
logic [3:0] d;
logic de;
} field1;
struct packed {
logic [3:0] d;
logic de;
} field3;
struct packed {
logic [3:0] d;
logic de;
} field4;
struct packed {
logic [3:0] d;
logic de;
} field5;
struct packed {
logic [3:0] d;
logic de;
} field6;
}
trial1_hw2reg_rwtype5_reg_t struct packed {
logic [31:0] d;
logic de;
}
trial1_hw2reg_rwtype6_reg_t struct packed {
logic [31:0] d;
}
trial1_hw2reg_rotype1_reg_t struct packed {
logic [31:0] d;
}
trial1_reg2hw_t struct packed {
trial1_reg2hw_rwtype0_reg_t rwtype0;
trial1_reg2hw_rwtype1_reg_t rwtype1;
trial1_reg2hw_rwtype2_reg_t rwtype2;
trial1_reg2hw_rwtype3_reg_t rwtype3;
trial1_reg2hw_rwtype4_reg_t rwtype4;
trial1_reg2hw_rotype0_reg_t rotype0;
trial1_reg2hw_w1ctype0_reg_t w1ctype0;
trial1_reg2hw_w1ctype1_reg_t w1ctype1;
trial1_reg2hw_w1ctype2_reg_t w1ctype2;
trial1_reg2hw_w1stype2_reg_t w1stype2;
trial1_reg2hw_w0ctype2_reg_t w0ctype2;
trial1_reg2hw_r0w1ctype2_reg_t r0w1ctype2;
trial1_reg2hw_rctype0_reg_t rctype0;
trial1_reg2hw_wotype0_reg_t wotype0;
trial1_reg2hw_mixtype0_reg_t mixtype0;
trial1_reg2hw_rwtype5_reg_t rwtype5;
trial1_reg2hw_rwtype6_reg_t rwtype6;
trial1_reg2hw_rotype1_reg_t rotype1;
}		 Register -> HW type
trial1_hw2reg_t struct packed {
trial1_hw2reg_rwtype2_reg_t rwtype2;
trial1_hw2reg_rwtype3_reg_t rwtype3;
trial1_hw2reg_rotype0_reg_t rotype0;
trial1_hw2reg_w1ctype2_reg_t w1ctype2;
trial1_hw2reg_w1stype2_reg_t w1stype2;
trial1_hw2reg_w0ctype2_reg_t w0ctype2;
trial1_hw2reg_r0w1ctype2_reg_t r0w1ctype2;
trial1_hw2reg_rctype0_reg_t rctype0;
trial1_hw2reg_mixtype0_reg_t mixtype0;
trial1_hw2reg_rwtype5_reg_t rwtype5;
trial1_hw2reg_rwtype6_reg_t rwtype6;
trial1_hw2reg_rotype1_reg_t rotype1;
}		 HW -> register type
trial1_id_e enum int {
TRIAL1_RWTYPE0,
TRIAL1_RWTYPE1,
TRIAL1_RWTYPE2,
TRIAL1_RWTYPE3,
TRIAL1_RWTYPE4,
TRIAL1_ROTYPE0,
TRIAL1_W1CTYPE0,
TRIAL1_W1CTYPE1,
TRIAL1_W1CTYPE2,
TRIAL1_W1STYPE2,
TRIAL1_W0CTYPE2,
TRIAL1_R0W1CTYPE2,
TRIAL1_RCTYPE0,
TRIAL1_WOTYPE0,
TRIAL1_MIXTYPE0,
TRIAL1_RWTYPE5,
TRIAL1_RWTYPE6,
TRIAL1_ROTYPE1,
TRIAL1_ROTYPE2,
TRIAL1_RWTYPE7 }		 Register index