Entity: trial1_reg_top

File: trial1_reg_top.sv

Diagram

Description

Copyright lowRISC contributors. Licensed under the Apache License, Version 2.0, see LICENSE for details. SPDX-License-Identifier: Apache-2.0

Ports

Port name	Direction	Description
clk_i	input
rst_ni	input
tl_i	input
tl_o	output
reg2hw	output	Write
hw2reg	input	Read
intg_err_o	output	Integrity check errors
devmode_i	input	If 1, explicit error return for unmapped register access

Signals

Name	Type	Description
reg_we	logic	register signals
reg_re	logic
reg_addr	logic [AW-1:0]
reg_wdata	logic [DW-1:0]
reg_be	logic [DBW-1:0]
reg_rdata	logic [DW-1:0]
reg_error	logic
addrmiss	logic
wr_err	logic
reg_rdata_next	logic [DW-1:0]
reg_busy	logic
tl_reg_h2d	tlul_pkg::tl_h2d_t
tl_reg_d2h	tlul_pkg::tl_d2h_t
intg_err	logic	incoming payload check
intg_err_q	logic
tl_o_pre	tlul_pkg::tl_d2h_t	outgoing integrity generation
rwtype0_we	logic	Define SW related signals Format: {wd
rwtype0_qs	logic [31:0]
rwtype0_wd	logic [31:0]
rwtype1_we	logic
rwtype1_field0_qs	logic
rwtype1_field0_wd	logic
rwtype1_field1_qs	logic
rwtype1_field1_wd	logic
rwtype1_field4_qs	logic
rwtype1_field4_wd	logic
rwtype1_field15_8_qs	logic [7:0]
rwtype1_field15_8_wd	logic [7:0]
rwtype2_we	logic
rwtype2_qs	logic [31:0]
rwtype2_wd	logic [31:0]
rwtype3_we	logic
rwtype3_field0_qs	logic [15:0]
rwtype3_field0_wd	logic [15:0]
rwtype3_field1_qs	logic [15:0]
rwtype3_field1_wd	logic [15:0]
rwtype4_we	logic
rwtype4_field0_qs	logic [15:0]
rwtype4_field0_wd	logic [15:0]
rwtype4_field1_qs	logic [15:0]
rwtype4_field1_wd	logic [15:0]
rotype0_qs	logic [31:0]
w1ctype0_we	logic
w1ctype0_qs	logic [31:0]
w1ctype0_wd	logic [31:0]
w1ctype1_we	logic
w1ctype1_field0_qs	logic [15:0]
w1ctype1_field0_wd	logic [15:0]
w1ctype1_field1_qs	logic [15:0]
w1ctype1_field1_wd	logic [15:0]
w1ctype2_we	logic
w1ctype2_qs	logic [31:0]
w1ctype2_wd	logic [31:0]
w1stype2_we	logic
w1stype2_qs	logic [31:0]
w1stype2_wd	logic [31:0]
w0ctype2_we	logic
w0ctype2_qs	logic [31:0]
w0ctype2_wd	logic [31:0]
r0w1ctype2_we	logic
r0w1ctype2_wd	logic [31:0]
rctype0_re	logic
rctype0_qs	logic [31:0]
rctype0_wd	logic [31:0]
wotype0_we	logic
wotype0_wd	logic [31:0]
mixtype0_we	logic
mixtype0_field0_qs	logic [3:0]
mixtype0_field0_wd	logic [3:0]
mixtype0_field1_qs	logic [3:0]
mixtype0_field1_wd	logic [3:0]
mixtype0_field2_qs	logic [3:0]
mixtype0_field3_qs	logic [3:0]
mixtype0_field4_qs	logic [3:0]
mixtype0_field4_wd	logic [3:0]
mixtype0_field5_qs	logic [3:0]
mixtype0_field5_wd	logic [3:0]
mixtype0_field6_qs	logic [3:0]
mixtype0_field6_wd	logic [3:0]
mixtype0_field7_wd	logic [3:0]
rwtype5_we	logic
rwtype5_qs	logic [31:0]
rwtype5_wd	logic [31:0]
rwtype6_re	logic
rwtype6_we	logic
rwtype6_qs	logic [31:0]
rwtype6_wd	logic [31:0]
rotype1_re	logic
rotype1_qs	logic [31:0]
rotype2_field0_qs	logic [7:0]
rotype2_field1_qs	logic [7:0]
rotype2_field2_qs	logic [11:0]
rwtype7_we	logic
rwtype7_qs	logic [31:0]
rwtype7_wd	logic [31:0]
addr_hit	logic [19:0]
shadow_busy	logic	shadow busy
reg_busy_sel	logic	register busy
unused_wdata	logic	Unused signal tieoff wdata / byte enable are not always fully used add a blanket unused statement to handle lint waivers
unused_be	logic

Constants

Name	Type	Value	Description
AW	int	10
DW	int	32
DBW	int	DW/8	Byte Width

Processes

unnamed: ( @(posedge clk_i or negedge rst_ni) )

Type: always_ff

unnamed: ( )

Type: always_comb

unnamed: ( )

Type: always_comb

Description
Check sub-word write is permitted

unnamed: ( )

Type: always_comb

Description
Read data return

unnamed: ( )

Type: always_comb

Instantiations

u_chk: tlul_cmd_intg_chk

u_rsp_intg_gen: tlul_rsp_intg_gen

u_reg_if: tlul_adapter_reg

u_rwtype0: prim_subreg

Description
Register instances
R[rwtype0]: V(False)

u_rwtype1_field0: prim_subreg

Description
R[rwtype1]: V(False)
F[field0]: 0:0

u_rwtype1_field1: prim_subreg

Description
F[field1]: 1:1

u_rwtype1_field4: prim_subreg

Description
F[field4]: 4:4

u_rwtype1_field15_8: prim_subreg

Description
F[field15_8]: 15:8

u_rwtype2: prim_subreg

Description
R[rwtype2]: V(False)

u_rwtype3_field0: prim_subreg

Description
R[rwtype3]: V(False)
F[field0]: 15:0

u_rwtype3_field1: prim_subreg

Description
F[field1]: 31:16

u_rwtype4_field0: prim_subreg

Description
R[rwtype4]: V(False)
F[field0]: 15:0

u_rwtype4_field1: prim_subreg

Description
F[field1]: 31:16

u_rotype0: prim_subreg

Description
R[rotype0]: V(False)

u_w1ctype0: prim_subreg

Description
R[w1ctype0]: V(False)

u_w1ctype1_field0: prim_subreg

Description
R[w1ctype1]: V(False)
F[field0]: 15:0

u_w1ctype1_field1: prim_subreg

Description
F[field1]: 31:16

u_w1ctype2: prim_subreg

Description
R[w1ctype2]: V(False)

u_w1stype2: prim_subreg

Description
R[w1stype2]: V(False)

u_w0ctype2: prim_subreg

Description
R[w0ctype2]: V(False)

u_r0w1ctype2: prim_subreg

Description
R[r0w1ctype2]: V(False)

u_rctype0: prim_subreg

Description
R[rctype0]: V(False)

u_wotype0: prim_subreg

Description
R[wotype0]: V(False)

u_mixtype0_field0: prim_subreg

Description
R[mixtype0]: V(False)
F[field0]: 3:0

u_mixtype0_field1: prim_subreg

Description
F[field1]: 7:4

u_mixtype0_field2: prim_subreg

Description
F[field2]: 11:8

u_mixtype0_field3: prim_subreg

Description
F[field3]: 15:12

u_mixtype0_field4: prim_subreg

Description
F[field4]: 19:16

u_mixtype0_field5: prim_subreg

Description
F[field5]: 23:20

u_mixtype0_field6: prim_subreg

Description
F[field6]: 27:24

u_mixtype0_field7: prim_subreg

Description
F[field7]: 31:28

u_rwtype5: prim_subreg

Description
R[rwtype5]: V(False)

u_rwtype6: prim_subreg_ext

Description
R[rwtype6]: V(True)

u_rotype1: prim_subreg_ext

Description
R[rotype1]: V(True)

u_rwtype7: prim_subreg

Description
R[rwtype7]: V(False)