Entity: usbdev_iomux

Diagram

clk_i rst_ni clk_usb_48mhz_i rst_usb_48mhz_ni usbdev_reg2hw_phy_pins_drive_reg_t sys_reg2hw_drive_i usbdev_reg2hw_phy_config_reg_t sys_reg2hw_config_i cio_usb_d_i cio_usb_dp_i cio_usb_dn_i cio_usb_sense_i usb_tx_d_i usb_tx_se0_i usb_tx_oe_i usb_pullup_en_i usb_suspend_i usbdev_hw2reg_phy_pins_sense_reg_t sys_hw2reg_sense_o sys_usb_sense_o cio_usb_d_o cio_usb_se0_o cio_usb_dp_o cio_usb_dn_o cio_usb_oe_o cio_usb_tx_mode_se_o cio_usb_dp_pullup_en_o cio_usb_dn_pullup_en_o cio_usb_suspend_o usb_rx_d_o usb_rx_dp_o usb_rx_dn_o usb_pwr_sense_o

Description

Copyright lowRISC contributors. Copyright ETH Zurich. Licensed under the Apache License, Version 2.0, see LICENSE for details. SPDX-License-Identifier: Apache-2.0

USB IO Mux

Muxes the USB IO signals from register access, differential signaling, single-ended signaling and swaps D+/D- if configured. The incomming signals are also muxed and synchronized to the corresponding clock domain.

Ports

Port name Direction Type Description
clk_i input
rst_ni input
clk_usb_48mhz_i input use usb_ prefix for signals in this clk
rst_usb_48mhz_ni input
sys_hw2reg_sense_o output usbdev_hw2reg_phy_pins_sense_reg_t Register interface (system clk)
sys_reg2hw_drive_i input usbdev_reg2hw_phy_pins_drive_reg_t
sys_reg2hw_config_i input usbdev_reg2hw_phy_config_reg_t
sys_usb_sense_o output
cio_usb_d_i input External USB Interface(s) (async)
cio_usb_dp_i input
cio_usb_dn_i input
cio_usb_d_o output
cio_usb_se0_o output
cio_usb_dp_o output
cio_usb_dn_o output
cio_usb_oe_o output
cio_usb_tx_mode_se_o output
cio_usb_sense_i input
cio_usb_dp_pullup_en_o output
cio_usb_dn_pullup_en_o output
cio_usb_suspend_o output
usb_rx_d_o output Internal USB Interface (usb clk)
usb_rx_dp_o output
usb_rx_dn_o output
usb_tx_d_i input
usb_tx_se0_i input
usb_tx_oe_i input
usb_pwr_sense_o output
usb_pullup_en_i input
usb_suspend_i input

Signals

Name Type Description
cio_usb_d_flipped logic
cio_usb_dp_pullup_en logic
cio_usb_dn_pullup_en logic
async_pwr_sense logic
sys_usb_sense logic
cio_usb_dp logic
cio_usb_dn logic
cio_usb_d logic
pinflip logic
unused_eop_single_bit logic
unused_rx_differential_mode logic
unused_usb_ref_disable logic
unused_tx_osc_test_mode logic

Processes

Type: always_comb

Type: always_comb

Description
Power sense mux

Instantiations

Description
////////
CDCs //
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USB pins sense (to sysclk)

Description
USB input pins (to usbclk)

Description
Use explicit muxes for the critical output signals, we do this
to avoid glitches from synthesized logic on these signals.
Clock muxes should be used here to achieve the best match between
rising and falling edges on an ASIC. This mismatch on the data line
degrades performance in the JK-KJ jitter test.