Entity: usbdev_reg_top

• File: usbdev_reg_top.sv

Diagram

Description

Ports

Port name	Direction	Type	Description
clk_i	input
rst_ni	input
tl_i	input
tl_o	output
tl_win_o	output		Output port for window
tl_win_i	input
reg2hw	output		Write
hw2reg	input		Read
intg_err_o	output		Integrity check errors
devmode_i	input		If 1, explicit error return for unmapped register access

Signals

Name	Type	Description
reg_we	logic	register signals
reg_re	logic
reg_addr	logic [AW-1:0]
reg_wdata	logic [DW-1:0]
reg_be	logic [DBW-1:0]
reg_rdata	logic [DW-1:0]
reg_error	logic
addrmiss	logic
wr_err	logic
reg_rdata_next	logic [DW-1:0]
reg_busy	logic
tl_reg_h2d	tlul_pkg::tl_h2d_t
tl_reg_d2h	tlul_pkg::tl_d2h_t
intg_err	logic	incoming payload check
intg_err_q	logic
tl_o_pre	tlul_pkg::tl_d2h_t	outgoing integrity generation
tl_socket_h2d	tlul_pkg::tl_h2d_t
tl_socket_d2h	tlul_pkg::tl_d2h_t
reg_steer	logic [1:0]
intr_state_we	logic	Define SW related signals Format: {wd
intr_state_pkt_received_qs	logic
intr_state_pkt_received_wd	logic
intr_state_pkt_sent_qs	logic
intr_state_pkt_sent_wd	logic
intr_state_disconnected_qs	logic
intr_state_disconnected_wd	logic
intr_state_host_lost_qs	logic
intr_state_host_lost_wd	logic
intr_state_link_reset_qs	logic
intr_state_link_reset_wd	logic
intr_state_link_suspend_qs	logic
intr_state_link_suspend_wd	logic
intr_state_link_resume_qs	logic
intr_state_link_resume_wd	logic
intr_state_av_empty_qs	logic
intr_state_av_empty_wd	logic
intr_state_rx_full_qs	logic
intr_state_rx_full_wd	logic
intr_state_av_overflow_qs	logic
intr_state_av_overflow_wd	logic
intr_state_link_in_err_qs	logic
intr_state_link_in_err_wd	logic
intr_state_rx_crc_err_qs	logic
intr_state_rx_crc_err_wd	logic
intr_state_rx_pid_err_qs	logic
intr_state_rx_pid_err_wd	logic
intr_state_rx_bitstuff_err_qs	logic
intr_state_rx_bitstuff_err_wd	logic
intr_state_frame_qs	logic
intr_state_frame_wd	logic
intr_state_connected_qs	logic
intr_state_connected_wd	logic
intr_state_link_out_err_qs	logic
intr_state_link_out_err_wd	logic
intr_enable_we	logic
intr_enable_pkt_received_qs	logic
intr_enable_pkt_received_wd	logic
intr_enable_pkt_sent_qs	logic
intr_enable_pkt_sent_wd	logic
intr_enable_disconnected_qs	logic
intr_enable_disconnected_wd	logic
intr_enable_host_lost_qs	logic
intr_enable_host_lost_wd	logic
intr_enable_link_reset_qs	logic
intr_enable_link_reset_wd	logic
intr_enable_link_suspend_qs	logic
intr_enable_link_suspend_wd	logic
intr_enable_link_resume_qs	logic
intr_enable_link_resume_wd	logic
intr_enable_av_empty_qs	logic
intr_enable_av_empty_wd	logic
intr_enable_rx_full_qs	logic
intr_enable_rx_full_wd	logic
intr_enable_av_overflow_qs	logic
intr_enable_av_overflow_wd	logic
intr_enable_link_in_err_qs	logic
intr_enable_link_in_err_wd	logic
intr_enable_rx_crc_err_qs	logic
intr_enable_rx_crc_err_wd	logic
intr_enable_rx_pid_err_qs	logic
intr_enable_rx_pid_err_wd	logic
intr_enable_rx_bitstuff_err_qs	logic
intr_enable_rx_bitstuff_err_wd	logic
intr_enable_frame_qs	logic
intr_enable_frame_wd	logic
intr_enable_connected_qs	logic
intr_enable_connected_wd	logic
intr_enable_link_out_err_qs	logic
intr_enable_link_out_err_wd	logic
intr_test_we	logic
intr_test_pkt_received_wd	logic
intr_test_pkt_sent_wd	logic
intr_test_disconnected_wd	logic
intr_test_host_lost_wd	logic
intr_test_link_reset_wd	logic
intr_test_link_suspend_wd	logic
intr_test_link_resume_wd	logic
intr_test_av_empty_wd	logic
intr_test_rx_full_wd	logic
intr_test_av_overflow_wd	logic
intr_test_link_in_err_wd	logic
intr_test_rx_crc_err_wd	logic
intr_test_rx_pid_err_wd	logic
intr_test_rx_bitstuff_err_wd	logic
intr_test_frame_wd	logic
intr_test_connected_wd	logic
intr_test_link_out_err_wd	logic
alert_test_we	logic
alert_test_wd	logic
usbctrl_we	logic
usbctrl_enable_qs	logic
usbctrl_enable_wd	logic
usbctrl_device_address_qs	logic [6:0]
usbctrl_device_address_wd	logic [6:0]
usbstat_re	logic
usbstat_frame_qs	logic [10:0]
usbstat_host_lost_qs	logic
usbstat_link_state_qs	logic [2:0]
usbstat_sense_qs	logic
usbstat_av_depth_qs	logic [2:0]
usbstat_av_full_qs	logic
usbstat_rx_depth_qs	logic [2:0]
usbstat_rx_empty_qs	logic
avbuffer_we	logic
avbuffer_wd	logic [4:0]
rxfifo_re	logic
rxfifo_buffer_qs	logic [4:0]
rxfifo_size_qs	logic [6:0]
rxfifo_setup_qs	logic
rxfifo_ep_qs	logic [3:0]
rxenable_setup_we	logic
rxenable_setup_setup_0_qs	logic
rxenable_setup_setup_0_wd	logic
rxenable_setup_setup_1_qs	logic
rxenable_setup_setup_1_wd	logic
rxenable_setup_setup_2_qs	logic
rxenable_setup_setup_2_wd	logic
rxenable_setup_setup_3_qs	logic
rxenable_setup_setup_3_wd	logic
rxenable_setup_setup_4_qs	logic
rxenable_setup_setup_4_wd	logic
rxenable_setup_setup_5_qs	logic
rxenable_setup_setup_5_wd	logic
rxenable_setup_setup_6_qs	logic
rxenable_setup_setup_6_wd	logic
rxenable_setup_setup_7_qs	logic
rxenable_setup_setup_7_wd	logic
rxenable_setup_setup_8_qs	logic
rxenable_setup_setup_8_wd	logic
rxenable_setup_setup_9_qs	logic
rxenable_setup_setup_9_wd	logic
rxenable_setup_setup_10_qs	logic
rxenable_setup_setup_10_wd	logic
rxenable_setup_setup_11_qs	logic
rxenable_setup_setup_11_wd	logic
rxenable_out_we	logic
rxenable_out_out_0_qs	logic
rxenable_out_out_0_wd	logic
rxenable_out_out_1_qs	logic
rxenable_out_out_1_wd	logic
rxenable_out_out_2_qs	logic
rxenable_out_out_2_wd	logic
rxenable_out_out_3_qs	logic
rxenable_out_out_3_wd	logic
rxenable_out_out_4_qs	logic
rxenable_out_out_4_wd	logic
rxenable_out_out_5_qs	logic
rxenable_out_out_5_wd	logic
rxenable_out_out_6_qs	logic
rxenable_out_out_6_wd	logic
rxenable_out_out_7_qs	logic
rxenable_out_out_7_wd	logic
rxenable_out_out_8_qs	logic
rxenable_out_out_8_wd	logic
rxenable_out_out_9_qs	logic
rxenable_out_out_9_wd	logic
rxenable_out_out_10_qs	logic
rxenable_out_out_10_wd	logic
rxenable_out_out_11_qs	logic
rxenable_out_out_11_wd	logic
in_sent_we	logic
in_sent_sent_0_qs	logic
in_sent_sent_0_wd	logic
in_sent_sent_1_qs	logic
in_sent_sent_1_wd	logic
in_sent_sent_2_qs	logic
in_sent_sent_2_wd	logic
in_sent_sent_3_qs	logic
in_sent_sent_3_wd	logic
in_sent_sent_4_qs	logic
in_sent_sent_4_wd	logic
in_sent_sent_5_qs	logic
in_sent_sent_5_wd	logic
in_sent_sent_6_qs	logic
in_sent_sent_6_wd	logic
in_sent_sent_7_qs	logic
in_sent_sent_7_wd	logic
in_sent_sent_8_qs	logic
in_sent_sent_8_wd	logic
in_sent_sent_9_qs	logic
in_sent_sent_9_wd	logic
in_sent_sent_10_qs	logic
in_sent_sent_10_wd	logic
in_sent_sent_11_qs	logic
in_sent_sent_11_wd	logic
stall_we	logic
stall_stall_0_qs	logic
stall_stall_0_wd	logic
stall_stall_1_qs	logic
stall_stall_1_wd	logic
stall_stall_2_qs	logic
stall_stall_2_wd	logic
stall_stall_3_qs	logic
stall_stall_3_wd	logic
stall_stall_4_qs	logic
stall_stall_4_wd	logic
stall_stall_5_qs	logic
stall_stall_5_wd	logic
stall_stall_6_qs	logic
stall_stall_6_wd	logic
stall_stall_7_qs	logic
stall_stall_7_wd	logic
stall_stall_8_qs	logic
stall_stall_8_wd	logic
stall_stall_9_qs	logic
stall_stall_9_wd	logic
stall_stall_10_qs	logic
stall_stall_10_wd	logic
stall_stall_11_qs	logic
stall_stall_11_wd	logic
configin_0_we	logic
configin_0_buffer_0_qs	logic [4:0]
configin_0_buffer_0_wd	logic [4:0]
configin_0_size_0_qs	logic [6:0]
configin_0_size_0_wd	logic [6:0]
configin_0_pend_0_qs	logic
configin_0_pend_0_wd	logic
configin_0_rdy_0_qs	logic
configin_0_rdy_0_wd	logic
configin_1_we	logic
configin_1_buffer_1_qs	logic [4:0]
configin_1_buffer_1_wd	logic [4:0]
configin_1_size_1_qs	logic [6:0]
configin_1_size_1_wd	logic [6:0]
configin_1_pend_1_qs	logic
configin_1_pend_1_wd	logic
configin_1_rdy_1_qs	logic
configin_1_rdy_1_wd	logic
configin_2_we	logic
configin_2_buffer_2_qs	logic [4:0]
configin_2_buffer_2_wd	logic [4:0]
configin_2_size_2_qs	logic [6:0]
configin_2_size_2_wd	logic [6:0]
configin_2_pend_2_qs	logic
configin_2_pend_2_wd	logic
configin_2_rdy_2_qs	logic
configin_2_rdy_2_wd	logic
configin_3_we	logic
configin_3_buffer_3_qs	logic [4:0]
configin_3_buffer_3_wd	logic [4:0]
configin_3_size_3_qs	logic [6:0]
configin_3_size_3_wd	logic [6:0]
configin_3_pend_3_qs	logic
configin_3_pend_3_wd	logic
configin_3_rdy_3_qs	logic
configin_3_rdy_3_wd	logic
configin_4_we	logic
configin_4_buffer_4_qs	logic [4:0]
configin_4_buffer_4_wd	logic [4:0]
configin_4_size_4_qs	logic [6:0]
configin_4_size_4_wd	logic [6:0]
configin_4_pend_4_qs	logic
configin_4_pend_4_wd	logic
configin_4_rdy_4_qs	logic
configin_4_rdy_4_wd	logic
configin_5_we	logic
configin_5_buffer_5_qs	logic [4:0]
configin_5_buffer_5_wd	logic [4:0]
configin_5_size_5_qs	logic [6:0]
configin_5_size_5_wd	logic [6:0]
configin_5_pend_5_qs	logic
configin_5_pend_5_wd	logic
configin_5_rdy_5_qs	logic
configin_5_rdy_5_wd	logic
configin_6_we	logic
configin_6_buffer_6_qs	logic [4:0]
configin_6_buffer_6_wd	logic [4:0]
configin_6_size_6_qs	logic [6:0]
configin_6_size_6_wd	logic [6:0]
configin_6_pend_6_qs	logic
configin_6_pend_6_wd	logic
configin_6_rdy_6_qs	logic
configin_6_rdy_6_wd	logic
configin_7_we	logic
configin_7_buffer_7_qs	logic [4:0]
configin_7_buffer_7_wd	logic [4:0]
configin_7_size_7_qs	logic [6:0]
configin_7_size_7_wd	logic [6:0]
configin_7_pend_7_qs	logic
configin_7_pend_7_wd	logic
configin_7_rdy_7_qs	logic
configin_7_rdy_7_wd	logic
configin_8_we	logic
configin_8_buffer_8_qs	logic [4:0]
configin_8_buffer_8_wd	logic [4:0]
configin_8_size_8_qs	logic [6:0]
configin_8_size_8_wd	logic [6:0]
configin_8_pend_8_qs	logic
configin_8_pend_8_wd	logic
configin_8_rdy_8_qs	logic
configin_8_rdy_8_wd	logic
configin_9_we	logic
configin_9_buffer_9_qs	logic [4:0]
configin_9_buffer_9_wd	logic [4:0]
configin_9_size_9_qs	logic [6:0]
configin_9_size_9_wd	logic [6:0]
configin_9_pend_9_qs	logic
configin_9_pend_9_wd	logic
configin_9_rdy_9_qs	logic
configin_9_rdy_9_wd	logic
configin_10_we	logic
configin_10_buffer_10_qs	logic [4:0]
configin_10_buffer_10_wd	logic [4:0]
configin_10_size_10_qs	logic [6:0]
configin_10_size_10_wd	logic [6:0]
configin_10_pend_10_qs	logic
configin_10_pend_10_wd	logic
configin_10_rdy_10_qs	logic
configin_10_rdy_10_wd	logic
configin_11_we	logic
configin_11_buffer_11_qs	logic [4:0]
configin_11_buffer_11_wd	logic [4:0]
configin_11_size_11_qs	logic [6:0]
configin_11_size_11_wd	logic [6:0]
configin_11_pend_11_qs	logic
configin_11_pend_11_wd	logic
configin_11_rdy_11_qs	logic
configin_11_rdy_11_wd	logic
iso_we	logic
iso_iso_0_qs	logic
iso_iso_0_wd	logic
iso_iso_1_qs	logic
iso_iso_1_wd	logic
iso_iso_2_qs	logic
iso_iso_2_wd	logic
iso_iso_3_qs	logic
iso_iso_3_wd	logic
iso_iso_4_qs	logic
iso_iso_4_wd	logic
iso_iso_5_qs	logic
iso_iso_5_wd	logic
iso_iso_6_qs	logic
iso_iso_6_wd	logic
iso_iso_7_qs	logic
iso_iso_7_wd	logic
iso_iso_8_qs	logic
iso_iso_8_wd	logic
iso_iso_9_qs	logic
iso_iso_9_wd	logic
iso_iso_10_qs	logic
iso_iso_10_wd	logic
iso_iso_11_qs	logic
iso_iso_11_wd	logic
data_toggle_clear_we	logic
data_toggle_clear_clear_0_wd	logic
data_toggle_clear_clear_1_wd	logic
data_toggle_clear_clear_2_wd	logic
data_toggle_clear_clear_3_wd	logic
data_toggle_clear_clear_4_wd	logic
data_toggle_clear_clear_5_wd	logic
data_toggle_clear_clear_6_wd	logic
data_toggle_clear_clear_7_wd	logic
data_toggle_clear_clear_8_wd	logic
data_toggle_clear_clear_9_wd	logic
data_toggle_clear_clear_10_wd	logic
data_toggle_clear_clear_11_wd	logic
phy_pins_sense_re	logic
phy_pins_sense_rx_dp_i_qs	logic
phy_pins_sense_rx_dn_i_qs	logic
phy_pins_sense_rx_d_i_qs	logic
phy_pins_sense_tx_dp_o_qs	logic
phy_pins_sense_tx_dn_o_qs	logic
phy_pins_sense_tx_d_o_qs	logic
phy_pins_sense_tx_se0_o_qs	logic
phy_pins_sense_tx_oe_o_qs	logic
phy_pins_sense_suspend_o_qs	logic
phy_pins_sense_pwr_sense_qs	logic
phy_pins_drive_we	logic
phy_pins_drive_dp_o_qs	logic
phy_pins_drive_dp_o_wd	logic
phy_pins_drive_dn_o_qs	logic
phy_pins_drive_dn_o_wd	logic
phy_pins_drive_d_o_qs	logic
phy_pins_drive_d_o_wd	logic
phy_pins_drive_se0_o_qs	logic
phy_pins_drive_se0_o_wd	logic
phy_pins_drive_oe_o_qs	logic
phy_pins_drive_oe_o_wd	logic
phy_pins_drive_tx_mode_se_o_qs	logic
phy_pins_drive_tx_mode_se_o_wd	logic
phy_pins_drive_dp_pullup_en_o_qs	logic
phy_pins_drive_dp_pullup_en_o_wd	logic
phy_pins_drive_dn_pullup_en_o_qs	logic
phy_pins_drive_dn_pullup_en_o_wd	logic
phy_pins_drive_suspend_o_qs	logic
phy_pins_drive_suspend_o_wd	logic
phy_pins_drive_en_qs	logic
phy_pins_drive_en_wd	logic
phy_config_we	logic
phy_config_rx_differential_mode_qs	logic
phy_config_rx_differential_mode_wd	logic
phy_config_tx_differential_mode_qs	logic
phy_config_tx_differential_mode_wd	logic
phy_config_eop_single_bit_qs	logic
phy_config_eop_single_bit_wd	logic
phy_config_override_pwr_sense_en_qs	logic
phy_config_override_pwr_sense_en_wd	logic
phy_config_override_pwr_sense_val_qs	logic
phy_config_override_pwr_sense_val_wd	logic
phy_config_pinflip_qs	logic
phy_config_pinflip_wd	logic
phy_config_usb_ref_disable_qs	logic
phy_config_usb_ref_disable_wd	logic
phy_config_tx_osc_test_mode_qs	logic
phy_config_tx_osc_test_mode_wd	logic
wake_config_we	logic
wake_config_wake_en_qs	logic
wake_config_wake_en_wd	logic
wake_config_wake_ack_qs	logic
wake_config_wake_ack_wd	logic
wake_debug_qs	logic [2:0]
addr_hit	logic [30:0]
shadow_busy	logic	shadow busy
reg_busy_sel	logic	register busy
unused_wdata	logic	Unused signal tieoff wdata / byte enable are not always fully used add a blanket unused statement to handle lint waivers
unused_be	logic

Constants

Name	Type	Value	Description
AW	int	12
DW	int	32
DBW	int	DW/8	Byte Width

Processes

• unnamed: ( @(posedge clk_i or negedge rst_ni) )

• unnamed: ( )

• unnamed: ( )

• unnamed: ( )

• unnamed: ( )

• unnamed: ( )

Instantiations

• u_chk: tlul_cmd_intg_chk

• u_rsp_intg_gen: tlul_rsp_intg_gen

• u_socket: tlul_socket_1n

• u_reg_if: tlul_adapter_reg

• u_intr_state_pkt_received: prim_subreg

• u_intr_state_pkt_sent: prim_subreg

• u_intr_state_disconnected: prim_subreg

• u_intr_state_host_lost: prim_subreg

• u_intr_state_link_reset: prim_subreg

• u_intr_state_link_suspend: prim_subreg

• u_intr_state_link_resume: prim_subreg

• u_intr_state_av_empty: prim_subreg

• u_intr_state_rx_full: prim_subreg

• u_intr_state_av_overflow: prim_subreg

• u_intr_state_link_in_err: prim_subreg

• u_intr_state_rx_crc_err: prim_subreg

• u_intr_state_rx_pid_err: prim_subreg

• u_intr_state_rx_bitstuff_err: prim_subreg

• u_intr_state_frame: prim_subreg

• u_intr_state_connected: prim_subreg

• u_intr_state_link_out_err: prim_subreg

• u_intr_enable_pkt_received: prim_subreg

• u_intr_enable_pkt_sent: prim_subreg

• u_intr_enable_disconnected: prim_subreg

• u_intr_enable_host_lost: prim_subreg

• u_intr_enable_link_reset: prim_subreg

• u_intr_enable_link_suspend: prim_subreg

• u_intr_enable_link_resume: prim_subreg

• u_intr_enable_av_empty: prim_subreg

• u_intr_enable_rx_full: prim_subreg

• u_intr_enable_av_overflow: prim_subreg

• u_intr_enable_link_in_err: prim_subreg

• u_intr_enable_rx_crc_err: prim_subreg

• u_intr_enable_rx_pid_err: prim_subreg

• u_intr_enable_rx_bitstuff_err: prim_subreg

• u_intr_enable_frame: prim_subreg

• u_intr_enable_connected: prim_subreg

• u_intr_enable_link_out_err: prim_subreg

• u_intr_test_pkt_received: prim_subreg_ext

• u_intr_test_pkt_sent: prim_subreg_ext

• u_intr_test_disconnected: prim_subreg_ext

• u_intr_test_host_lost: prim_subreg_ext

• u_intr_test_link_reset: prim_subreg_ext

• u_intr_test_link_suspend: prim_subreg_ext

• u_intr_test_link_resume: prim_subreg_ext

• u_intr_test_av_empty: prim_subreg_ext

• u_intr_test_rx_full: prim_subreg_ext

• u_intr_test_av_overflow: prim_subreg_ext

• u_intr_test_link_in_err: prim_subreg_ext

• u_intr_test_rx_crc_err: prim_subreg_ext

• u_intr_test_rx_pid_err: prim_subreg_ext

• u_intr_test_rx_bitstuff_err: prim_subreg_ext

• u_intr_test_frame: prim_subreg_ext

• u_intr_test_connected: prim_subreg_ext

• u_intr_test_link_out_err: prim_subreg_ext

• u_alert_test: prim_subreg_ext

• u_usbctrl_enable: prim_subreg

• u_usbctrl_device_address: prim_subreg

• u_usbstat_frame: prim_subreg_ext

• u_usbstat_host_lost: prim_subreg_ext

• u_usbstat_link_state: prim_subreg_ext

• u_usbstat_sense: prim_subreg_ext

• u_usbstat_av_depth: prim_subreg_ext

• u_usbstat_av_full: prim_subreg_ext

• u_usbstat_rx_depth: prim_subreg_ext

• u_usbstat_rx_empty: prim_subreg_ext

• u_avbuffer: prim_subreg

• u_rxfifo_buffer: prim_subreg_ext

• u_rxfifo_size: prim_subreg_ext

• u_rxfifo_setup: prim_subreg_ext

• u_rxfifo_ep: prim_subreg_ext

• u_phy_pins_sense_rx_dp_i: prim_subreg_ext

• u_phy_pins_sense_rx_dn_i: prim_subreg_ext

• u_phy_pins_sense_rx_d_i: prim_subreg_ext

• u_phy_pins_sense_tx_dp_o: prim_subreg_ext

• u_phy_pins_sense_tx_dn_o: prim_subreg_ext

• u_phy_pins_sense_tx_d_o: prim_subreg_ext

• u_phy_pins_sense_tx_se0_o: prim_subreg_ext

• u_phy_pins_sense_tx_oe_o: prim_subreg_ext

• u_phy_pins_sense_suspend_o: prim_subreg_ext

• u_phy_pins_sense_pwr_sense: prim_subreg_ext

• u_phy_pins_drive_dp_o: prim_subreg

• u_phy_pins_drive_dn_o: prim_subreg

• u_phy_pins_drive_d_o: prim_subreg

• u_phy_pins_drive_se0_o: prim_subreg

• u_phy_pins_drive_oe_o: prim_subreg

• u_phy_pins_drive_tx_mode_se_o: prim_subreg

• u_phy_pins_drive_dp_pullup_en_o: prim_subreg

• u_phy_pins_drive_dn_pullup_en_o: prim_subreg

• u_phy_pins_drive_suspend_o: prim_subreg

• u_phy_pins_drive_en: prim_subreg

• u_phy_config_rx_differential_mode: prim_subreg

• u_phy_config_tx_differential_mode: prim_subreg

• u_phy_config_eop_single_bit: prim_subreg

• u_phy_config_override_pwr_sense_en: prim_subreg

• u_phy_config_override_pwr_sense_val: prim_subreg

• u_phy_config_pinflip: prim_subreg

• u_phy_config_usb_ref_disable: prim_subreg

• u_phy_config_tx_osc_test_mode: prim_subreg

• u_wake_config_wake_en: prim_subreg

• u_wake_config_wake_ack: prim_subreg

• u_wake_debug: prim_subreg