Entity: axi_axil_adapter

Diagram

ADDR_WIDTH AXI_DATA_WIDTH AXI_STRB_WIDTH AXI_ID_WIDTH AXIL_DATA_WIDTH AXIL_STRB_WIDTH CONVERT_BURST CONVERT_NARROW_BURST wire clk wire rst wire [AXI_ID_WIDTH-1:0] s_axi_awid wire [ADDR_WIDTH-1:0] s_axi_awaddr wire [7:0] s_axi_awlen wire [2:0] s_axi_awsize wire [1:0] s_axi_awburst wire s_axi_awlock wire [3:0] s_axi_awcache wire [2:0] s_axi_awprot wire s_axi_awvalid wire [AXI_DATA_WIDTH-1:0] s_axi_wdata wire [AXI_STRB_WIDTH-1:0] s_axi_wstrb wire s_axi_wlast wire s_axi_wvalid wire s_axi_bready wire [AXI_ID_WIDTH-1:0] s_axi_arid wire [ADDR_WIDTH-1:0] s_axi_araddr wire [7:0] s_axi_arlen wire [2:0] s_axi_arsize wire [1:0] s_axi_arburst wire s_axi_arlock wire [3:0] s_axi_arcache wire [2:0] s_axi_arprot wire s_axi_arvalid wire s_axi_rready wire m_axil_awready wire m_axil_wready wire [1:0] m_axil_bresp wire m_axil_bvalid wire m_axil_arready wire [AXIL_DATA_WIDTH-1:0] m_axil_rdata wire [1:0] m_axil_rresp wire m_axil_rvalid wire s_axi_awready wire s_axi_wready wire [AXI_ID_WIDTH-1:0] s_axi_bid wire [1:0] s_axi_bresp wire s_axi_bvalid wire s_axi_arready wire [AXI_ID_WIDTH-1:0] s_axi_rid wire [AXI_DATA_WIDTH-1:0] s_axi_rdata wire [1:0] s_axi_rresp wire s_axi_rlast wire s_axi_rvalid wire [ADDR_WIDTH-1:0] m_axil_awaddr wire [2:0] m_axil_awprot wire m_axil_awvalid wire [AXIL_DATA_WIDTH-1:0] m_axil_wdata wire [AXIL_STRB_WIDTH-1:0] m_axil_wstrb wire m_axil_wvalid wire m_axil_bready wire [ADDR_WIDTH-1:0] m_axil_araddr wire [2:0] m_axil_arprot wire m_axil_arvalid wire m_axil_rready

Description

Language: Verilog 2001

Generics

Generic name Type Value Description
ADDR_WIDTH 32 Width of address bus in bits
AXI_DATA_WIDTH 32 Width of input (slave) AXI interface data bus in bits
AXI_STRB_WIDTH undefined Width of input (slave) AXI interface wstrb (width of data bus in words)
AXI_ID_WIDTH 8 Width of AXI ID signal
AXIL_DATA_WIDTH 32 Width of output (master) AXI lite interface data bus in bits
AXIL_STRB_WIDTH undefined Width of output (master) AXI lite interface wstrb (width of data bus in words)
CONVERT_BURST 1 When adapting to a wider bus, re-pack full-width burst instead of passing through narrow burst if possible
CONVERT_NARROW_BURST 0 When adapting to a wider bus, re-pack all bursts instead of passing through narrow burst if possible

Ports

Port name Direction Type Description
clk input wire
rst input wire
s_axi_awid input wire [AXI_ID_WIDTH-1:0] * AXI slave interface */
s_axi_awaddr input wire [ADDR_WIDTH-1:0]
s_axi_awlen input wire [7:0]
s_axi_awsize input wire [2:0]
s_axi_awburst input wire [1:0]
s_axi_awlock input wire
s_axi_awcache input wire [3:0]
s_axi_awprot input wire [2:0]
s_axi_awvalid input wire
s_axi_awready output wire
s_axi_wdata input wire [AXI_DATA_WIDTH-1:0]
s_axi_wstrb input wire [AXI_STRB_WIDTH-1:0]
s_axi_wlast input wire
s_axi_wvalid input wire
s_axi_wready output wire
s_axi_bid output wire [AXI_ID_WIDTH-1:0]
s_axi_bresp output wire [1:0]
s_axi_bvalid output wire
s_axi_bready input wire
s_axi_arid input wire [AXI_ID_WIDTH-1:0]
s_axi_araddr input wire [ADDR_WIDTH-1:0]
s_axi_arlen input wire [7:0]
s_axi_arsize input wire [2:0]
s_axi_arburst input wire [1:0]
s_axi_arlock input wire
s_axi_arcache input wire [3:0]
s_axi_arprot input wire [2:0]
s_axi_arvalid input wire
s_axi_arready output wire
s_axi_rid output wire [AXI_ID_WIDTH-1:0]
s_axi_rdata output wire [AXI_DATA_WIDTH-1:0]
s_axi_rresp output wire [1:0]
s_axi_rlast output wire
s_axi_rvalid output wire
s_axi_rready input wire
m_axil_awaddr output wire [ADDR_WIDTH-1:0] * AXI lite master interface */
m_axil_awprot output wire [2:0]
m_axil_awvalid output wire
m_axil_awready input wire
m_axil_wdata output wire [AXIL_DATA_WIDTH-1:0]
m_axil_wstrb output wire [AXIL_STRB_WIDTH-1:0]
m_axil_wvalid output wire
m_axil_wready input wire
m_axil_bresp input wire [1:0]
m_axil_bvalid input wire
m_axil_bready output wire
m_axil_araddr output wire [ADDR_WIDTH-1:0]
m_axil_arprot output wire [2:0]
m_axil_arvalid output wire
m_axil_arready input wire
m_axil_rdata input wire [AXIL_DATA_WIDTH-1:0]
m_axil_rresp input wire [1:0]
m_axil_rvalid input wire
m_axil_rready output wire

Instantiations