Entity: axi_crossbar

Diagram

S_COUNT M_COUNT DATA_WIDTH ADDR_WIDTH STRB_WIDTH S_ID_WIDTH M_ID_WIDTH AWUSER_ENABLE AWUSER_WIDTH WUSER_ENABLE WUSER_WIDTH BUSER_ENABLE BUSER_WIDTH ARUSER_ENABLE ARUSER_WIDTH RUSER_ENABLE RUSER_WIDTH S_THREADS S_ACCEPT M_REGIONS M_BASE_ADDR M_ADDR_WIDTH M_CONNECT_READ M_CONNECT_WRITE M_ISSUE M_SECURE S_AW_REG_TYPE S_W_REG_TYPE S_B_REG_TYPE S_AR_REG_TYPE S_R_REG_TYPE M_AW_REG_TYPE M_W_REG_TYPE M_B_REG_TYPE M_AR_REG_TYPE M_R_REG_TYPE wire clk wire rst wire [S_COUNT*S_ID_WIDTH-1:0] s_axi_awid wire [S_COUNT*ADDR_WIDTH-1:0] s_axi_awaddr wire [S_COUNT*8-1:0] s_axi_awlen wire [S_COUNT*3-1:0] s_axi_awsize wire [S_COUNT*2-1:0] s_axi_awburst wire [S_COUNT-1:0] s_axi_awlock wire [S_COUNT*4-1:0] s_axi_awcache wire [S_COUNT*3-1:0] s_axi_awprot wire [S_COUNT*4-1:0] s_axi_awqos wire [S_COUNT*AWUSER_WIDTH-1:0] s_axi_awuser wire [S_COUNT-1:0] s_axi_awvalid wire [S_COUNT*DATA_WIDTH-1:0] s_axi_wdata wire [S_COUNT*STRB_WIDTH-1:0] s_axi_wstrb wire [S_COUNT-1:0] s_axi_wlast wire [S_COUNT*WUSER_WIDTH-1:0] s_axi_wuser wire [S_COUNT-1:0] s_axi_wvalid wire [S_COUNT-1:0] s_axi_bready wire [S_COUNT*S_ID_WIDTH-1:0] s_axi_arid wire [S_COUNT*ADDR_WIDTH-1:0] s_axi_araddr wire [S_COUNT*8-1:0] s_axi_arlen wire [S_COUNT*3-1:0] s_axi_arsize wire [S_COUNT*2-1:0] s_axi_arburst wire [S_COUNT-1:0] s_axi_arlock wire [S_COUNT*4-1:0] s_axi_arcache wire [S_COUNT*3-1:0] s_axi_arprot wire [S_COUNT*4-1:0] s_axi_arqos wire [S_COUNT*ARUSER_WIDTH-1:0] s_axi_aruser wire [S_COUNT-1:0] s_axi_arvalid wire [S_COUNT-1:0] s_axi_rready wire [M_COUNT-1:0] m_axi_awready wire [M_COUNT-1:0] m_axi_wready wire [M_COUNT*M_ID_WIDTH-1:0] m_axi_bid wire [M_COUNT*2-1:0] m_axi_bresp wire [M_COUNT*BUSER_WIDTH-1:0] m_axi_buser wire [M_COUNT-1:0] m_axi_bvalid wire [M_COUNT-1:0] m_axi_arready wire [M_COUNT*M_ID_WIDTH-1:0] m_axi_rid wire [M_COUNT*DATA_WIDTH-1:0] m_axi_rdata wire [M_COUNT*2-1:0] m_axi_rresp wire [M_COUNT-1:0] m_axi_rlast wire [M_COUNT*RUSER_WIDTH-1:0] m_axi_ruser wire [M_COUNT-1:0] m_axi_rvalid wire [S_COUNT-1:0] s_axi_awready wire [S_COUNT-1:0] s_axi_wready wire [S_COUNT*S_ID_WIDTH-1:0] s_axi_bid wire [S_COUNT*2-1:0] s_axi_bresp wire [S_COUNT*BUSER_WIDTH-1:0] s_axi_buser wire [S_COUNT-1:0] s_axi_bvalid wire [S_COUNT-1:0] s_axi_arready wire [S_COUNT*S_ID_WIDTH-1:0] s_axi_rid wire [S_COUNT*DATA_WIDTH-1:0] s_axi_rdata wire [S_COUNT*2-1:0] s_axi_rresp wire [S_COUNT-1:0] s_axi_rlast wire [S_COUNT*RUSER_WIDTH-1:0] s_axi_ruser wire [S_COUNT-1:0] s_axi_rvalid wire [M_COUNT*M_ID_WIDTH-1:0] m_axi_awid wire [M_COUNT*ADDR_WIDTH-1:0] m_axi_awaddr wire [M_COUNT*8-1:0] m_axi_awlen wire [M_COUNT*3-1:0] m_axi_awsize wire [M_COUNT*2-1:0] m_axi_awburst wire [M_COUNT-1:0] m_axi_awlock wire [M_COUNT*4-1:0] m_axi_awcache wire [M_COUNT*3-1:0] m_axi_awprot wire [M_COUNT*4-1:0] m_axi_awqos wire [M_COUNT*4-1:0] m_axi_awregion wire [M_COUNT*AWUSER_WIDTH-1:0] m_axi_awuser wire [M_COUNT-1:0] m_axi_awvalid wire [M_COUNT*DATA_WIDTH-1:0] m_axi_wdata wire [M_COUNT*STRB_WIDTH-1:0] m_axi_wstrb wire [M_COUNT-1:0] m_axi_wlast wire [M_COUNT*WUSER_WIDTH-1:0] m_axi_wuser wire [M_COUNT-1:0] m_axi_wvalid wire [M_COUNT-1:0] m_axi_bready wire [M_COUNT*M_ID_WIDTH-1:0] m_axi_arid wire [M_COUNT*ADDR_WIDTH-1:0] m_axi_araddr wire [M_COUNT*8-1:0] m_axi_arlen wire [M_COUNT*3-1:0] m_axi_arsize wire [M_COUNT*2-1:0] m_axi_arburst wire [M_COUNT-1:0] m_axi_arlock wire [M_COUNT*4-1:0] m_axi_arcache wire [M_COUNT*3-1:0] m_axi_arprot wire [M_COUNT*4-1:0] m_axi_arqos wire [M_COUNT*4-1:0] m_axi_arregion wire [M_COUNT*ARUSER_WIDTH-1:0] m_axi_aruser wire [M_COUNT-1:0] m_axi_arvalid wire [M_COUNT-1:0] m_axi_rready

Description

Language: Verilog 2001

Generics

Generic name Type Value Description
S_COUNT 4 Number of AXI inputs (slave interfaces)
M_COUNT 4 Number of AXI outputs (master interfaces)
DATA_WIDTH 32 Width of data bus in bits
ADDR_WIDTH 32 Width of address bus in bits
STRB_WIDTH undefined Width of wstrb (width of data bus in words)
S_ID_WIDTH 8 Input ID field width (from AXI masters)
M_ID_WIDTH S_ID_WIDTH+$clog2(S_COUNT) Output ID field width (towards AXI slaves) Additional bits required for response routing
AWUSER_ENABLE 0 Propagate awuser signal
AWUSER_WIDTH 1 Width of awuser signal
WUSER_ENABLE 0 Propagate wuser signal
WUSER_WIDTH 1 Width of wuser signal
BUSER_ENABLE 0 Propagate buser signal
BUSER_WIDTH 1 Width of buser signal
ARUSER_ENABLE 0 Propagate aruser signal
ARUSER_WIDTH 1 Width of aruser signal
RUSER_ENABLE 0 Propagate ruser signal
RUSER_WIDTH 1 Width of ruser signal
S_THREADS undefined Number of concurrent unique IDs for each slave interface S_COUNT concatenated fields of 32 bits
S_ACCEPT undefined Number of concurrent operations for each slave interface S_COUNT concatenated fields of 32 bits
M_REGIONS 1 Number of regions per master interface
M_BASE_ADDR 0 Master interface base addresses M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_WIDTH bits set to zero for default addressing based on M_ADDR_WIDTH
M_ADDR_WIDTH undefined Master interface address widths M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
M_CONNECT_READ undefined Read connections between interfaces M_COUNT concatenated fields of S_COUNT bits
M_CONNECT_WRITE undefined Write connections between interfaces M_COUNT concatenated fields of S_COUNT bits
M_ISSUE undefined Number of concurrent operations for each master interface M_COUNT concatenated fields of 32 bits
M_SECURE undefined Secure master (fail operations based on awprot/arprot) M_COUNT bits
S_AW_REG_TYPE undefined Slave interface AW channel register type (input) 0 to bypass, 1 for simple buffer, 2 for skid buffer
S_W_REG_TYPE undefined Slave interface W channel register type (input) 0 to bypass, 1 for simple buffer, 2 for skid buffer
S_B_REG_TYPE undefined Slave interface B channel register type (output) 0 to bypass, 1 for simple buffer, 2 for skid buffer
S_AR_REG_TYPE undefined Slave interface AR channel register type (input) 0 to bypass, 1 for simple buffer, 2 for skid buffer
S_R_REG_TYPE undefined Slave interface R channel register type (output) 0 to bypass, 1 for simple buffer, 2 for skid buffer
M_AW_REG_TYPE undefined Master interface AW channel register type (output) 0 to bypass, 1 for simple buffer, 2 for skid buffer
M_W_REG_TYPE undefined Master interface W channel register type (output) 0 to bypass, 1 for simple buffer, 2 for skid buffer
M_B_REG_TYPE undefined Master interface B channel register type (input) 0 to bypass, 1 for simple buffer, 2 for skid buffer
M_AR_REG_TYPE undefined Master interface AR channel register type (output) 0 to bypass, 1 for simple buffer, 2 for skid buffer
M_R_REG_TYPE undefined Master interface R channel register type (input) 0 to bypass, 1 for simple buffer, 2 for skid buffer

Ports

Port name Direction Type Description
clk input wire
rst input wire
s_axi_awid input wire [S_COUNT*S_ID_WIDTH-1:0] * AXI slave interfaces */
s_axi_awaddr input wire [S_COUNT*ADDR_WIDTH-1:0]
s_axi_awlen input wire [S_COUNT*8-1:0]
s_axi_awsize input wire [S_COUNT*3-1:0]
s_axi_awburst input wire [S_COUNT*2-1:0]
s_axi_awlock input wire [S_COUNT-1:0]
s_axi_awcache input wire [S_COUNT*4-1:0]
s_axi_awprot input wire [S_COUNT*3-1:0]
s_axi_awqos input wire [S_COUNT*4-1:0]
s_axi_awuser input wire [S_COUNT*AWUSER_WIDTH-1:0]
s_axi_awvalid input wire [S_COUNT-1:0]
s_axi_awready output wire [S_COUNT-1:0]
s_axi_wdata input wire [S_COUNT*DATA_WIDTH-1:0]
s_axi_wstrb input wire [S_COUNT*STRB_WIDTH-1:0]
s_axi_wlast input wire [S_COUNT-1:0]
s_axi_wuser input wire [S_COUNT*WUSER_WIDTH-1:0]
s_axi_wvalid input wire [S_COUNT-1:0]
s_axi_wready output wire [S_COUNT-1:0]
s_axi_bid output wire [S_COUNT*S_ID_WIDTH-1:0]
s_axi_bresp output wire [S_COUNT*2-1:0]
s_axi_buser output wire [S_COUNT*BUSER_WIDTH-1:0]
s_axi_bvalid output wire [S_COUNT-1:0]
s_axi_bready input wire [S_COUNT-1:0]
s_axi_arid input wire [S_COUNT*S_ID_WIDTH-1:0]
s_axi_araddr input wire [S_COUNT*ADDR_WIDTH-1:0]
s_axi_arlen input wire [S_COUNT*8-1:0]
s_axi_arsize input wire [S_COUNT*3-1:0]
s_axi_arburst input wire [S_COUNT*2-1:0]
s_axi_arlock input wire [S_COUNT-1:0]
s_axi_arcache input wire [S_COUNT*4-1:0]
s_axi_arprot input wire [S_COUNT*3-1:0]
s_axi_arqos input wire [S_COUNT*4-1:0]
s_axi_aruser input wire [S_COUNT*ARUSER_WIDTH-1:0]
s_axi_arvalid input wire [S_COUNT-1:0]
s_axi_arready output wire [S_COUNT-1:0]
s_axi_rid output wire [S_COUNT*S_ID_WIDTH-1:0]
s_axi_rdata output wire [S_COUNT*DATA_WIDTH-1:0]
s_axi_rresp output wire [S_COUNT*2-1:0]
s_axi_rlast output wire [S_COUNT-1:0]
s_axi_ruser output wire [S_COUNT*RUSER_WIDTH-1:0]
s_axi_rvalid output wire [S_COUNT-1:0]
s_axi_rready input wire [S_COUNT-1:0]
m_axi_awid output wire [M_COUNT*M_ID_WIDTH-1:0] * AXI master interfaces */
m_axi_awaddr output wire [M_COUNT*ADDR_WIDTH-1:0]
m_axi_awlen output wire [M_COUNT*8-1:0]
m_axi_awsize output wire [M_COUNT*3-1:0]
m_axi_awburst output wire [M_COUNT*2-1:0]
m_axi_awlock output wire [M_COUNT-1:0]
m_axi_awcache output wire [M_COUNT*4-1:0]
m_axi_awprot output wire [M_COUNT*3-1:0]
m_axi_awqos output wire [M_COUNT*4-1:0]
m_axi_awregion output wire [M_COUNT*4-1:0]
m_axi_awuser output wire [M_COUNT*AWUSER_WIDTH-1:0]
m_axi_awvalid output wire [M_COUNT-1:0]
m_axi_awready input wire [M_COUNT-1:0]
m_axi_wdata output wire [M_COUNT*DATA_WIDTH-1:0]
m_axi_wstrb output wire [M_COUNT*STRB_WIDTH-1:0]
m_axi_wlast output wire [M_COUNT-1:0]
m_axi_wuser output wire [M_COUNT*WUSER_WIDTH-1:0]
m_axi_wvalid output wire [M_COUNT-1:0]
m_axi_wready input wire [M_COUNT-1:0]
m_axi_bid input wire [M_COUNT*M_ID_WIDTH-1:0]
m_axi_bresp input wire [M_COUNT*2-1:0]
m_axi_buser input wire [M_COUNT*BUSER_WIDTH-1:0]
m_axi_bvalid input wire [M_COUNT-1:0]
m_axi_bready output wire [M_COUNT-1:0]
m_axi_arid output wire [M_COUNT*M_ID_WIDTH-1:0]
m_axi_araddr output wire [M_COUNT*ADDR_WIDTH-1:0]
m_axi_arlen output wire [M_COUNT*8-1:0]
m_axi_arsize output wire [M_COUNT*3-1:0]
m_axi_arburst output wire [M_COUNT*2-1:0]
m_axi_arlock output wire [M_COUNT-1:0]
m_axi_arcache output wire [M_COUNT*4-1:0]
m_axi_arprot output wire [M_COUNT*3-1:0]
m_axi_arqos output wire [M_COUNT*4-1:0]
m_axi_arregion output wire [M_COUNT*4-1:0]
m_axi_aruser output wire [M_COUNT*ARUSER_WIDTH-1:0]
m_axi_arvalid output wire [M_COUNT-1:0]
m_axi_arready input wire [M_COUNT-1:0]
m_axi_rid input wire [M_COUNT*M_ID_WIDTH-1:0]
m_axi_rdata input wire [M_COUNT*DATA_WIDTH-1:0]
m_axi_rresp input wire [M_COUNT*2-1:0]
m_axi_rlast input wire [M_COUNT-1:0]
m_axi_ruser input wire [M_COUNT*RUSER_WIDTH-1:0]
m_axi_rvalid input wire [M_COUNT-1:0]
m_axi_rready output wire [M_COUNT-1:0]

Instantiations