Entity: axil_cdc

Diagram

DATA_WIDTH ADDR_WIDTH STRB_WIDTH wire s_clk wire s_rst wire [ADDR_WIDTH-1:0] s_axil_awaddr wire [2:0] s_axil_awprot wire s_axil_awvalid wire [DATA_WIDTH-1:0] s_axil_wdata wire [STRB_WIDTH-1:0] s_axil_wstrb wire s_axil_wvalid wire s_axil_bready wire [ADDR_WIDTH-1:0] s_axil_araddr wire [2:0] s_axil_arprot wire s_axil_arvalid wire s_axil_rready wire m_clk wire m_rst wire m_axil_awready wire m_axil_wready wire [1:0] m_axil_bresp wire m_axil_bvalid wire m_axil_arready wire [DATA_WIDTH-1:0] m_axil_rdata wire [1:0] m_axil_rresp wire m_axil_rvalid wire s_axil_awready wire s_axil_wready wire [1:0] s_axil_bresp wire s_axil_bvalid wire s_axil_arready wire [DATA_WIDTH-1:0] s_axil_rdata wire [1:0] s_axil_rresp wire s_axil_rvalid wire [ADDR_WIDTH-1:0] m_axil_awaddr wire [2:0] m_axil_awprot wire m_axil_awvalid wire [DATA_WIDTH-1:0] m_axil_wdata wire [STRB_WIDTH-1:0] m_axil_wstrb wire m_axil_wvalid wire m_axil_bready wire [ADDR_WIDTH-1:0] m_axil_araddr wire [2:0] m_axil_arprot wire m_axil_arvalid wire m_axil_rready

Description

Language: Verilog 2001

Generics

Generic name Type Value Description
DATA_WIDTH 32 Width of data bus in bits
ADDR_WIDTH 32 Width of address bus in bits
STRB_WIDTH undefined Width of wstrb (width of data bus in words)

Ports

Port name Direction Type Description
s_clk input wire * AXI lite slave interface */
s_rst input wire
s_axil_awaddr input wire [ADDR_WIDTH-1:0]
s_axil_awprot input wire [2:0]
s_axil_awvalid input wire
s_axil_awready output wire
s_axil_wdata input wire [DATA_WIDTH-1:0]
s_axil_wstrb input wire [STRB_WIDTH-1:0]
s_axil_wvalid input wire
s_axil_wready output wire
s_axil_bresp output wire [1:0]
s_axil_bvalid output wire
s_axil_bready input wire
s_axil_araddr input wire [ADDR_WIDTH-1:0]
s_axil_arprot input wire [2:0]
s_axil_arvalid input wire
s_axil_arready output wire
s_axil_rdata output wire [DATA_WIDTH-1:0]
s_axil_rresp output wire [1:0]
s_axil_rvalid output wire
s_axil_rready input wire
m_clk input wire * AXI lite master interface */
m_rst input wire
m_axil_awaddr output wire [ADDR_WIDTH-1:0]
m_axil_awprot output wire [2:0]
m_axil_awvalid output wire
m_axil_awready input wire
m_axil_wdata output wire [DATA_WIDTH-1:0]
m_axil_wstrb output wire [STRB_WIDTH-1:0]
m_axil_wvalid output wire
m_axil_wready input wire
m_axil_bresp input wire [1:0]
m_axil_bvalid input wire
m_axil_bready output wire
m_axil_araddr output wire [ADDR_WIDTH-1:0]
m_axil_arprot output wire [2:0]
m_axil_arvalid output wire
m_axil_arready input wire
m_axil_rdata input wire [DATA_WIDTH-1:0]
m_axil_rresp input wire [1:0]
m_axil_rvalid input wire
m_axil_rready output wire

Instantiations