Entity: T80

Diagram

integer Mode integer IOWait integer Flag_C integer Flag_N integer Flag_P integer Flag_X integer Flag_H integer Flag_Y integer Flag_Z integer Flag_S std_logic RESET_n std_logic CLK_n std_logic CEN std_logic WAIT_n std_logic INT_n std_logic NMI_n std_logic BUSRQ_n std_logic_vector(7 downto 0) DInst std_logic_vector(7 downto 0) DI std_logic out0 std_logic DIRSet std_logic_vector(211 downto 0) DIR std_logic M1_n std_logic IORQ std_logic NoRead std_logic Write std_logic RFSH_n std_logic HALT_n std_logic BUSAK_n std_logic_vector(15 downto 0) A std_logic_vector(7 downto 0) DO std_logic_vector(2 downto 0) MC std_logic_vector(2 downto 0) TS std_logic IntCycle_n std_logic IntE std_logic Stop std_logic_vector(211 downto 0) REG

Description

T80(c) core. Attempt to finish all undocumented features and provide accurate timings. Version 350. Copyright (c) 2018 Sorgelig Test passed: ZEXDOC, ZEXALL, Z80Full(), Z80memptr () Currently only SCF and CCF instructions aren't passed X/Y flags check as correct implementation is still unclear.

T80(b) core. In an effort to merge and maintain bug fixes ….

Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010 Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle Ver 300 started tidyup.

MikeJ March 2005 Latest version from www.fpgaarcade.com (original www.opencores.org)

Z80 compatible microprocessor core

Version : 0247 Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) All rights reserved

Redistribution and use in source and synthezised forms, with or without modification, are permitted provided that the following conditions are met:

Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.

Redistributions in synthesized form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.

Neither the name of the author nor the names of other contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Please report bugs to the author, but before you do so, please make sure that this is not a derivative work and that you have the latest version of this file.

The latest version of this file can be found at: http://www.opencores.org/cvsweb.shtml/t80/

Limitations :

File history :

 0208 : First complete release  0210 : Fixed wait and halt  0211 : Fixed Refresh addition and IM 1  0214 : Fixed mostly flags, only the block instructions now fail the zex regression test  0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson  0235 : Added clock enable and IM 2 fix by Mike Johnson  0237 : Changed 8080 I/O address output, added IntE output  0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag  0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode  0242 : Added I/O wait, fixed refresh address, moved some registers to RAM  0247 : Fixed bus req/ack cycle

Generics

Generic name Type Value Description
Mode integer 0 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait integer 0 0 => Single cycle I/O, 1 => Std I/O cycle
Flag_C integer 0
Flag_N integer 1
Flag_P integer 2
Flag_X integer 3
Flag_H integer 4
Flag_Y integer 5
Flag_Z integer 6
Flag_S integer 7

Ports

Port name Direction Type Description
RESET_n in std_logic
CLK_n in std_logic
CEN in std_logic
WAIT_n in std_logic
INT_n in std_logic
NMI_n in std_logic
BUSRQ_n in std_logic
M1_n out std_logic
IORQ out std_logic
NoRead out std_logic
Write out std_logic
RFSH_n out std_logic
HALT_n out std_logic
BUSAK_n out std_logic
A out std_logic_vector(15 downto 0)
DInst in std_logic_vector(7 downto 0)
DI in std_logic_vector(7 downto 0)
DO out std_logic_vector(7 downto 0)
MC out std_logic_vector(2 downto 0)
TS out std_logic_vector(2 downto 0)
IntCycle_n out std_logic
IntE out std_logic
Stop out std_logic
out0 in std_logic 0 => OUT(C),0, 1 => OUT(C),255
REG out std_logic_vector(211 downto 0) IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
DIRSet in std_logic
DIR in std_logic_vector(211 downto 0) IFF2, IFF1, IM, IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A

Signals

Name Type Description
ACC std_logic_vector(7 downto 0)
F std_logic_vector(7 downto 0)
Ap std_logic_vector(7 downto 0)
Fp std_logic_vector(7 downto 0)
I std_logic_vector(7 downto 0)
R unsigned(7 downto 0)
SP unsigned(15 downto 0)
PC unsigned(15 downto 0)
RegDIH std_logic_vector(7 downto 0)
RegDIL std_logic_vector(7 downto 0)
RegBusA std_logic_vector(15 downto 0)
RegBusB std_logic_vector(15 downto 0)
RegBusC std_logic_vector(15 downto 0)
RegAddrA_r std_logic_vector(2 downto 0)
RegAddrA std_logic_vector(2 downto 0)
RegAddrB_r std_logic_vector(2 downto 0)
RegAddrB std_logic_vector(2 downto 0)
RegAddrC std_logic_vector(2 downto 0)
RegWEH std_logic
RegWEL std_logic
Alternate std_logic
WZ std_logic_vector(15 downto 0) MEMPTR register
IR std_logic_vector(7 downto 0) Instruction register
ISet std_logic_vector(1 downto 0) Instruction set selector
RegBusA_r std_logic_vector(15 downto 0)
ID16 signed(15 downto 0)
Save_Mux std_logic_vector(7 downto 0)
TState unsigned(2 downto 0)
MCycle std_logic_vector(2 downto 0)
IntE_FF1 std_logic
IntE_FF2 std_logic
Halt_FF std_logic
BusReq_s std_logic
BusAck std_logic
ClkEn std_logic
NMI_s std_logic
IStatus std_logic_vector(1 downto 0)
DI_Reg std_logic_vector(7 downto 0)
T_Res std_logic
XY_State std_logic_vector(1 downto 0)
Pre_XY_F_M std_logic_vector(2 downto 0)
NextIs_XY_Fetch std_logic
XY_Ind std_logic
No_BTR std_logic
BTR_r std_logic
Auto_Wait std_logic
Auto_Wait_t1 std_logic
Auto_Wait_t2 std_logic
IncDecZ std_logic
BusB std_logic_vector(7 downto 0) ALU signals
BusA std_logic_vector(7 downto 0)
ALU_Q std_logic_vector(7 downto 0)
F_Out std_logic_vector(7 downto 0)
Read_To_Reg_r std_logic_vector(4 downto 0) Registered micro code outputs
Arith16_r std_logic
Z16_r std_logic
ALU_Op_r std_logic_vector(3 downto 0)
Save_ALU_r std_logic
PreserveC_r std_logic
MCycles std_logic_vector(2 downto 0)
MCycles_d std_logic_vector(2 downto 0) Micro code outputs
TStates std_logic_vector(2 downto 0)
IntCycle std_logic
NMICycle std_logic
Inc_PC std_logic
Inc_WZ std_logic
IncDec_16 std_logic_vector(3 downto 0)
Prefix std_logic_vector(1 downto 0)
Read_To_Acc std_logic
Read_To_Reg std_logic
Set_BusB_To std_logic_vector(3 downto 0)
Set_BusA_To std_logic_vector(3 downto 0)
ALU_Op std_logic_vector(3 downto 0)
Save_ALU std_logic
PreserveC std_logic
Arith16 std_logic
Set_Addr_To std_logic_vector(2 downto 0)
Jump std_logic
JumpE std_logic
JumpXY std_logic
Call std_logic
RstP std_logic
LDZ std_logic
LDW std_logic
LDSPHL std_logic
IORQ_i std_logic
Special_LD std_logic_vector(2 downto 0)
ExchangeDH std_logic
ExchangeRp std_logic
ExchangeAF std_logic
ExchangeRS std_logic
I_DJNZ std_logic
I_CPL std_logic
I_CCF std_logic
I_SCF std_logic
I_RETN std_logic
I_BT std_logic
I_BC std_logic
I_BTR std_logic
I_RLD std_logic
I_RRD std_logic
I_RXDD std_logic
I_INRC std_logic
SetWZ std_logic_vector(1 downto 0)
SetDI std_logic
SetEI std_logic
IMode std_logic_vector(1 downto 0)
Halt std_logic
XYbit_undoc std_logic
DOR std_logic_vector(127 downto 0)
ABus std_logic_vector(15 downto 0)
ABus_last std_logic_vector(15 downto 0)
NoRead_int std_logic
Write_int std_logic

Processes

Description
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BC('), DE('), HL('), IX and IY
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Description
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Buses
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Description
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Generate external control signals
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Description
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Main state machine
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Instantiations