Entity: jt49_noise

Diagram

wire cen wire clk wire rst_n wire[4:0] period noise

Description

Th

Ports

Port name Direction Type Description
cen input wire
clk input wire
rst_n input wire
period input wire[4:0]
noise output

Signals

Name Type Description
count reg[5:0]
poly17 reg[16:0]
poly17_zero wire
noise_en wire
last_en reg
noise_up wire

Processes

Type: always

Type: always

Instantiations