Entity: specdrum

Diagram

wire clock wire ce wire iorq wire wr wire[7:0] d wire[7:4] a [7:0] q

Description


Ports

Port name Direction Type Description
clock input wire
ce input wire
iorq input wire
wr input wire
d input wire[7:0]
q output [7:0]
a input wire[7:4]

Processes

Type: always

Description