Entity: gamma_regs

Diagram

integer AXI_ADDR_WIDTH std_logic axi_aclk std_logic axi_aresetn std_logic_vector(31 downto 0) version_value virtual_bus axilite std_logic version_strobe std_logic gamma_strobe std_logic_vector(15 downto 0) gamma_value

Description

OFFSETLABELR/WSCDESCRIPTIONRESET VALUE
0x0000IP_VERSION
[31:0] VersionRNOversion info.VERSION
0x0004IP_CORE
[31:0] IDRNOId Info.ID
0x0008gamma0x7fffffff
[15:0] gammaR/WNOgamma value
OFFSETLABELR/WSCDESCRIPTIONRESET VALUE
:---------------------------:-------------------------------------------------------------------
0x0000IP_VERSION
[31:0] VersionRNOversion info.VERSION
0x0004IP_CORE
[31:0] IDRNOId Info.ID
0x0008gamma0x7fffffff
[15:0] gammaR/WNOgamma value

Generics

Generic name Type Value Description
AXI_ADDR_WIDTH integer 32

Ports

Port name Direction Type Description
axi_aclk in std_logic
axi_aresetn in std_logic
version_strobe out std_logic
version_value in std_logic_vector(31 downto 0)
gamma_strobe out std_logic
gamma_value out std_logic_vector(15 downto 0)
axilite in Virtual bus

Virtual Buses

axilite

Port name Direction Type Description
s_axi_awaddr in std_logic_vector(AXI_ADDR_WIDTH - 1 downto 0)
s_axi_awprot in std_logic_vector(2 downto 0)
s_axi_awvalid in std_logic
s_axi_awready out std_logic
s_axi_wdata in std_logic_vector(31 downto 0)
s_axi_wstrb in std_logic_vector(3 downto 0)
s_axi_wvalid in std_logic
s_axi_wready out std_logic
s_axi_araddr in std_logic_vector(AXI_ADDR_WIDTH - 1 downto 0)
s_axi_arprot in std_logic_vector(2 downto 0)
s_axi_arvalid in std_logic
s_axi_arready out std_logic
s_axi_rdata out std_logic_vector(31 downto 0)
s_axi_rresp out std_logic_vector(1 downto 0)
s_axi_rvalid out std_logic
s_axi_rready in std_logic
s_axi_bresp out std_logic_vector(1 downto 0)
s_axi_bvalid out std_logic
s_axi_bready in std_logic

Signals

Name Type Description
s_axi_awready_r std_logic
s_axi_wready_r std_logic
s_axi_awaddr_reg_r unsigned(s_axi_awaddr'range)
s_axi_bvalid_r std_logic
s_axi_bresp_r std_logic_vector(s_axi_bresp'range)
s_axi_arready_r std_logic
s_axi_araddr_reg_r unsigned(s_axi_araddr'range)
s_axi_rvalid_r std_logic
s_axi_rresp_r std_logic_vector(s_axi_rresp'range)
s_axi_wdata_reg_r std_logic_vector(s_axi_wdata'range)
s_axi_wstrb_reg_r std_logic_vector(s_axi_wstrb'range)
s_axi_rdata_r std_logic_vector(s_axi_rdata'range)
s_version_strobe_r std_logic
s_reg_version_value std_logic_vector(31 downto 0)
s_gamma_strobe_r std_logic
s_reg_gamma_value_r std_logic_vector(15 downto 0)

Constants

Name Type Value Description
AXI_OKAY std_logic_vector(1 downto 0) "00"
AXI_DECERR std_logic_vector(1 downto 0) "11"
c_addr_bits natural 16

Processes

State machines

state transitions cluster_v_state_r v_state_r IDLE IDLE READ_REGISTER READ_REGISTER IDLE->READ_REGISTER s_axi_arvalid = '1'    READ_RESPONSE READ_RESPONSE READ_REGISTER->READ_RESPONSE s_axi_araddr_reg_r(c_addr_bits-1 downto 0) = resize(VERSION_OFFSET, c_addr_bits)    READ_REGISTER->READ_RESPONSE s_axi_araddr_reg_r(c_addr_bits-1 downto 0) = resize(  GAMMA_OFFSET, c_addr_bits)    READ_REGISTER->READ_RESPONSE not ()    WAIT_MEMORY_RDATA WAIT_MEMORY_RDATA WAIT_MEMORY_RDATA->READ_RESPONSE v_mem_wait_count_r = MEM_WAIT_COUNT-1    DONE DONE READ_RESPONSE->DONE DONE->IDLE s_axi_rready = '1'   
state transitions cluster_v_state_r v_state_r IDLE IDLE ADDR_FIRST ADDR_FIRST IDLE->ADDR_FIRST s_axi_awvalid = '1'    DATA_FIRST DATA_FIRST IDLE->DATA_FIRST s_axi_wvalid = '1'    UPDATE_REGISTER UPDATE_REGISTER IDLE->UPDATE_REGISTER s_axi_awvalid = '1' and s_axi_wvalid = '1'    ADDR_FIRST->UPDATE_REGISTER s_axi_wvalid = '1'    DATA_FIRST->UPDATE_REGISTER s_axi_awvalid = '1'    DONE DONE UPDATE_REGISTER->DONE DONE->IDLE s_axi_bready = '1'