Entity: gamma_top

Copyright: 2021
This file is part of gamma_c.
gamma_c is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
gamma_c is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with gamma_c. If not, see https://www.gnu.org/licenses/.
Author: Ismael Pérez Rojo (ismaelprojo@gmail.com)

Diagram

Módulo para la codificación de imágenes capturadas con scannerCompresión de datos

Generic name	Type	Value	Description
G_DATA_IN	integer	12	Data bits in
G_DATA_OUT	integer	8	Data bits out
AXI_ADDR_WIDTH	integer	32

Port name	Direction	Type	Description
clk	in	std_logic	Reloj del sistema
reset	in	std_logic	Reset nivel alto
dv_in	in	std_logic	Data valid in
data_in	in	std_logic_vector(G_DATA_IN - 1 downto 0)	Dato de entrada del ADC
dv_out	out	std_logic	Data valid de salida
data_out	out	std_logic_vector(G_DATA_OUT - 1 downto 0)	Data out
axi_aclk	in	std_logic
axi_aresetn	in	std_logic
axilite	in	Virtual bus

Port name	Direction	Type
s_axi_awaddr	in	std_logic_vector(AXI_ADDR_WIDTH - 1 downto 0)
s_axi_awprot	in	std_logic_vector(2 downto 0)
s_axi_awvalid	in	std_logic
s_axi_awready	out	std_logic
s_axi_wdata	in	std_logic_vector(31 downto 0)
s_axi_wstrb	in	std_logic_vector(3 downto 0)
s_axi_wvalid	in	std_logic
s_axi_wready	out	std_logic
s_axi_araddr	in	std_logic_vector(AXI_ADDR_WIDTH - 1 downto 0)
s_axi_arprot	in	std_logic_vector(2 downto 0)
s_axi_arvalid	in	std_logic
s_axi_arready	out	std_logic
s_axi_rdata	out	std_logic_vector(31 downto 0)
s_axi_rresp	out	std_logic_vector(1 downto 0)
s_axi_rvalid	out	std_logic
s_axi_rready	in	std_logic
s_axi_bresp	out	std_logic_vector(1 downto 0)
s_axi_bvalid	out	std_logic
s_axi_bready	in	std_logic

Name	Type	Description
gamma_in	std_logic_vector(15 downto 0)