Class TEMPLATE_NAME_VERILOG

Templates types for Verilog/SV

Hierarchy

  • TEMPLATE_NAME_VERILOG

Constructors

Properties

key: string
value: any
COCOTB: {
    description: string;
    id: string;
    lang: LANG;
    name: string;
} = ...

Type declaration

  • description: string
  • id: string
  • lang: LANG
  • name: string
HDL_ELEMENT_INSTANCE: {
    description: string;
    id: string;
    lang: LANG;
    name: string;
} = ...

Type declaration

  • description: string
  • id: string
  • lang: LANG
  • name: string
HDL_ELEMENT_MIX_INSTANCE: {
    description: string;
    id: string;
    lang: LANG;
    name: string;
} = ...

Type declaration

  • description: string
  • id: string
  • lang: LANG
  • name: string
HDL_ELEMENT_MIX_TESTBENCH_NORMAL: {
    description: string;
    id: string;
    lang: LANG;
    name: string;
} = ...

Type declaration

  • description: string
  • id: string
  • lang: LANG
  • name: string
HDL_ELEMENT_MIX_TESTBENCH_VUNIT: {
    description: string;
    id: string;
    lang: LANG;
    name: string;
} = ...

Type declaration

  • description: string
  • id: string
  • lang: LANG
  • name: string
HDL_ELEMENT_SIGNAL: {
    description: string;
    id: string;
    lang: LANG;
    name: string;
} = ...

Type declaration

  • description: string
  • id: string
  • lang: LANG
  • name: string
TESTBENCH_NORMAL: {
    description: string;
    id: string;
    lang: LANG;
    name: string;
} = ...

Type declaration

  • description: string
  • id: string
  • lang: LANG
  • name: string
TESTBENCH_VUNIT: {
    description: string;
    id: string;
    lang: LANG;
    name: string;
} = ...

Type declaration

  • description: string
  • id: string
  • lang: LANG
  • name: string

Methods

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