Templates

Template	SV/Verilog	VHDL	Description
Testbench	Yes	Yes	HDL testbench
VUnit Testbench	Yes	Yes	HDL VUnit testbench
cocotb	Yes	Yes	cocotb python example
Signals	Yes	Yes	Port as signals
Component	Yes	Yes	Entity as component declaration
Instance	Yes	Yes	Entity as instance declaration
Instance	Yes	Yes
Cross language instance	Yes	Yes
Cross language testbench	Yes	Yes
Cross language VUnit testbench	Yes	Yes
Verilator	Yes	No	Verilator C++ example

Step by step

1. Open a Verilog/SV/VHDL file and push the template generation button.

Image 1: Step 0

2. Select the desired template from the list.

Image 1: Step 1

3. The template will be stored in the clipboard and ready to be pasted Ctrl+v anywhere.

caution

Make sure that the cursor is in the editor view. So TerosHDL can detect the active document

VHDL

Verilog