Source view
Adding source
Action | Description |
---|---|
From browser | Select files from browser. |
From CSV | Add files from a CSV list |
From VUnit | Add files from a VUnit run.py |
The accepted CSV format is as follows:
file_0.sv
file_1.vhd
file_2.vhd
or
lib_0, file_1.vhd
file_2.vhd
lib_0, file_3.vhd
Source configuration
You can configure the properties of a project source. You can set the file type, language version, and type.
Languages | Description |
---|---|
vhdlSource | VHDL |
verilogSource | Verilog |
systemVerilogSource | SystemVerilog |
cSource | C |
cppSource | C++ |
python | Python |
veribleLintRules | Verible Linter Rules |
tclSource | TCL |
xdc | Xilinx Vivado constraint file |
sdc | Constraints File |
pin | Pin declaration |
xci | Xilinx Vivado IP file |
sbyConfigTemplate | SymbiYosys |
osvvmProject | OSVVM Project |
QIP | Intel Quartus IP file |
UCF | Xilinx ISE constraint file |
IP | IP declaration |
QSYS | Quartus IP |
none |
Languages | Versions |
---|---|
VHDL | 2008, 2000, 93 |
Verilog/SV | 2005, 2000 |
Source Type | Versions |
---|---|
Simulation | Testbenches |
Synthesis | Synthesizable Sources |
None | Not specified |
Adding library
Adding source to library
Deleting source/library
Setting project toplevel file
When you select a file as toplevel in the project you can see (current)
at the end of the name.