Verilog/SV elements
note
by default, the documenter will use //!
to recognize things to document.
Supported labels
Here are the following labels supported by the documenter:
- Module Description
- Ports
- Parameters
- Constants
- Registers / Wires
- Always Block
- Instances
- Functions
- Typedefs
Module
- Code
- Result
//! @title mymodule design
//! @author terosHDL
module mymodule #(
parameter PARAM1 = 1024 //! number of bytes in fifo
)(
output reg [PARAM1-1:0] data,
input clk, //! 300Mhz Clock
input rstn
);
endmodule
![Documentation result](/terosHDLdoc/assets/images/module-ffb6a053f68cf68a1056b6c563468c62.png)
Ports
- Code
- Result
//! @title mymodule design
//! @author terosHDL
module mymodule #(
parameter PARAM1 = 1024 //! number of bytes in fifo
)(
output reg [PARAM1-1:0] data,
input clk, //! 300Mhz Clock
input rstn
);
endmodule
![Documentation result](/terosHDLdoc/assets/images/port-cfa92d03d24c7417b8a2bc5d4021347d.png)
Parameters
- Code
- Result
//! @title mymodule design
//! @author terosHDL
module mymodule #(
parameter PARAM1 = 1024 //! number of bytes in fifo
)(
output reg [PARAM1-1:0] data,
input clk, //! 300Mhz Clock
input rstn
);
endmodule
![Documentation result](/terosHDLdoc/assets/images/parameter-219aff3d61813a84e8424e3b38d2911b.png)
Constants
- Code
- Result
module myconsts ();
localparam SN=11223344; //! SN for this node
endmodule
![Documentation result](/terosHDLdoc/assets/images/const-c485728550614ffecac790ea4ff38dd9.png)
Always
- Code
- Result
module alwaysmod (
input clk,
input rstn
);
always @(posedge clk or negedge rstn) begin: myproc
end
endmodule
![Documentation result](/terosHDLdoc/assets/images/always-efa0af3aae3a28db31f5a924ef0989ff.png)
Instances
- Code
- Result
module tb_mytb(
input clk,
input rstn
);
mymodule dut(
.rstn (rstn),
.clk (clk)
);
endmodule
Functions
- Code
- Result
module funcs ;
function reg[1:0] myfunc(input a,b);
myfunc = {a,b};
endfunction
endmodule
![Documentation result](/terosHDLdoc/assets/images/functions-3c3d052657d363391516d72d39fa6303.png)
Typedefs
- Code
- Result
//! AXI-4 Stream
typedef struct packed {
logic [7:0] data;
logic [0:0] valid;
logic [0:0] clk;
} mystruct;
![Documentation result](/terosHDLdoc/assets/images/typedef-4463b491c4838c92f1d034032e2c7034.png)