VHDL elements
note
by default, the documenter will use --!
to recognize things to document.
Supported labels
Here are the following labels supported by the documenter:
- Entity description
- Ports
- Generics
- Constants
- Signals
- Processes
- Instances
- Functions
- Types
Entity
- Code
- Result
--! Entity example
-- description
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity myentity is
generic (
gen1 : integer := 0
);
port (
clk : in std_logic;
reset : in std_logic
);
end entity;
architecture rtl of myentity is
begin
end architecture;
![Documentation result](/terosHDLdoc/assets/images/entity-034af8c86e69a90947dcd79aaa52b485.png)
Package
- Code
- Result
package mynewpackage is
end package;
![Documentation result](/terosHDLdoc/assets/images/port-51de9e1f0fd6a374ea648b3decf6f837.png)
Generic
- Code
- Result
--! Entity example
-- description
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity myentity is
generic (
gen1 : integer := 0
);
port (
clk : in std_logic;
reset : in std_logic
);
end entity;
architecture rtl of myentity is
begin
end architecture;
![Documentation result](/terosHDLdoc/assets/images/generic-d46391a8cc75e94e258c1b7c8ef76ac7.png)
Port
- Code
- Result
entity ports is
port (
clk : in std_logic; --! my clock
reset : in std_logic --! reset of everything
);
end entity;
![Documentation result](/terosHDLdoc/assets/images/port-51de9e1f0fd6a374ea648b3decf6f837.png)
Signal
- Code
- Result
library ieee;
use ieee.std_logic_1164.all;
entity mysignal is
port (
clk : in std_logic;
reset : in std_logic
);
end entity mysignal;
architecture rtl of mysignal is
signal sig_a : std_logic_vector(31 downto 0);
signal sig_b : std_logic_vector(31 downto 0);
signal sig_c : std_logic; --! example documentation
signal data_a: integer range 0 to 1023;
begin
end architecture;
![Documentation result](/terosHDLdoc/assets/images/signal-9b3c6d34ce80b8ad6d806addfebec319.png)
Constant
- Code
- Result
package mypackage is
constant DATA_WIDTH : integer := 35; --! number of bits
constant ADDR_WIDTH : integer := 21; --! number of bits
end package;
![Documentation result](/terosHDLdoc/assets/images/constant-2fb468dcf8abb6ad5b0c4e448361020a.png)
Function
- Code
- Result
library ieee;
use ieee.std_logic_1164.all;
package mypackage is
function func1 (x:integer) return std_logic;
end package;
package body mypackage is
function func1 (x:integer) return std_logic is
begin
end function;
end package body;
Process
- Code
- Result
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity my_process is
port (
clk : in std_logic;
reset : in std_logic
);
end entity my_process;
architecture rtl of my_process is
begin
myproc: process (clk)
begin
end process;
end architecture;
Type
- Code
- Result
library ieee;
use ieee.std_logic_1164.all;
package mytypes is
type main_sm_type is (IDLE,PUSHA,PUSHB,FINISH); --! main state machine states
end package;
![Documentation result](/terosHDLdoc/assets/images/tp-7f0d8b5898850ee9ddde851fb19573e1.png)