Documentation for:

Generated by TerosHDL © 2020-2021 License GPLv3
Carlos Alberto Ruiz Naranjo (carlosruiznaranjo@gmail.com)
Ismael Perez Rojo (ismaelprojo@gmail.com)

Project revision 2021-09-06 13:30:40

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/home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/syncTrigStream/hdl/syncTrigStream_logic.vhd syncTrigStream_logic.vhd /home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/syncTrigStream/hdl/syncTrigStream.vhd->/home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/syncTrigStream/hdl/syncTrigStream_logic.vhd /home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/syncTrigStream/hdl/syncTrigStream_sync_bit.vhd syncTrigStream_sync_bit.vhd /home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/syncTrigStream/hdl/syncTrigStream.vhd->/home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/syncTrigStream/hdl/syncTrigStream_sync_bit.vhd /home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/syncTrigStream/hdl/syncTrigStream_sync_vector.vhd syncTrigStream_sync_vector.vhd /home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/syncTrigStream/hdl/syncTrigStream.vhd->/home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/syncTrigStream/hdl/syncTrigStream_sync_vector.vhd /home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/syncTrigStream/simulation/top_syncTrigStream.vhd top_syncTrigStream.vhd /home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/syncTrigStream/simulation/top_syncTrigStream.vhd->/home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/syncTrigStream/hdl/syncTrigStream_logic.vhd /home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/windowReal/hdl/wb_windowReal.vhd wb_windowReal.vhd /home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/windowReal/hdl/windowReal.vhd windowReal.vhd /home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/windowReal/hdl/windowReal.vhd->/home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/windowReal/hdl/wb_windowReal.vhd /home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/windowReal/hdl/windowReal_handComm.vhd windowReal_handComm.vhd /home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/windowReal/hdl/windowReal.vhd->/home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/windowReal/hdl/windowReal_handComm.vhd /home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/windowReal/hdl/windowReal_logic.vhd windowReal_logic.vhd /home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/windowReal/hdl/windowReal.vhd->/home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/windowReal/hdl/windowReal_logic.vhd /home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/windowReal/hdl/windowReal_ram.vhd windowReal_ram.vhd /home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/windowReal/hdl/windowReal_logic.vhd->/home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/windowReal/hdl/windowReal_ram.vhd /home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/windowReal/simulation/top_windowReal_tb.vhd top_windowReal_tb.vhd /home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/windowReal/simulation/top_windowReal_tb.vhd->/home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/windowReal/hdl/windowReal_logic.vhd /home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/windowReal/simulation/top_windowReal_tb.vhd->/home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/windowReal/simulation/ram_storage16.vhd /home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/windowReal/simulation/top_windowReal_tb.vhd->/home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/windowReal/simulation/readFromFile.vhd /home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/windowReal/simulation/windowReal_tb.vhd windowReal_tb.vhd /home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/windowReal/simulation/windowReal_tb.vhd->/home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/windowReal/simulation/ram_storage16.vhd /home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/windowReal/simulation/windowReal_tb.vhd->/home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/windowReal/simulation/readFromFile.vhd /home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/xcorr_prn_slow_complex/hdl/xcorr_prn_slow_complex.vhd xcorr_prn_slow_complex.vhd /home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/xcorr_prn_slow_complex/hdl/xcorr_prn_slow_complex_mux.vhd xcorr_prn_slow_complex_mux.vhd /home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/xcorr_prn_slow_complex/hdl/xcorr_prn_slow_complex.vhd->/home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/xcorr_prn_slow_complex/hdl/xcorr_prn_slow_complex_mux.vhd /home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/xcorr_prn_slow_complex/hdl/xcorr_prn_slow_complex_correl.vhd xcorr_prn_slow_complex_correl.vhd /home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/xcorr_prn_slow_complex/hdl/xcorr_prn_slow_complex_mux.vhd->/home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/xcorr_prn_slow_complex/hdl/xcorr_prn_slow_complex_correl.vhd /home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/xcorr_prn_slow_complex/hdl/xcorr_prn_slow_complex_ram.vhd xcorr_prn_slow_complex_ram.vhd /home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/xcorr_prn_slow_complex/hdl/xcorr_prn_slow_complex_mux.vhd->/home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/xcorr_prn_slow_complex/hdl/xcorr_prn_slow_complex_ram.vhd /home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/xcorr_prn_slow_complex/simulation/top_xcorr_prn_slow_complex_tb.vhd top_xcorr_prn_slow_complex_tb.vhd /home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/xcorr_prn_slow_complex/simulation/top_xcorr_prn_slow_complex_tb.vhd->/home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/cacode/hdl/cacode.vhd /home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/xcorr_prn_slow_complex/simulation/top_xcorr_prn_slow_complex_tb.vhd->/home/runner/work/teroshdl-documenter-demo/teroshdl-documenter-demo/fpga_ip/xcorr_prn_slow_complex/hdl/xcorr_prn_slow_complex.vhd

Designs